Semiconductor growth substrates and associated systems and methods for die singulation

US8951842B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-8951842-B2
Application numberUS-201213349432-A
CountryUS
Kind codeB2
Filing dateJan 12, 2012
Priority dateJan 12, 2012
Publication dateFeb 10, 2015
Grant dateFeb 10, 2015

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

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  7. Citations and related patents

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Abstract

Official abstract text for this publication.

Semiconductor growth substrates and associated systems and methods for die singulation are disclosed. A representative method for manufacturing semiconductor devices includes forming spaced-apart structures at a dicing street located between neighboring device growth regions of a substrate material. The method can further include epitaxially growing a semiconductor material by adding a first portion of semiconductor material to the device growth regions and adding a second portion of semiconductor material to the structures. The method can still further include forming semiconductor devices at the device growth regions, and separating the semiconductor devices from each other at the dicing street by removing the spaced-apart structures and the underlying substrate material at the dicing street.

First claim

Opening claim text (preview).

We claim: 1. A method for manufacturing LEDs, comprising: applying an aluminum nitride seed material to a growth substrate to form multiple LED growth regions with a dicing street between neighboring growth regions; at the dicing street, removing portions of the seed material to expose the growth substrate, leaving spaced-apart dummy structures at the dicing street; epitaxially growing gallium nitride on the aluminum nitride seed material by: adding a first portion of gallium nitride to the growth regions; and adding a second portion of gallium nitride to the spaced-apart structures, wherein the second portion of the gallium nitride would otherwise be disposed at the device growth regions in the absence of the spaced-apart structures; forming LEDs with the gallium nitride at the growth regions; and separating the LEDs from each at the dicing street by removing the dummy structures and the underlying growth substrate at the dicing street. 2. The method of claim 1 wherein forming the spaced-apart structures includes forming a first structure closest to one of the growth regions, and wherein the first structure is spaced apart from the one growth region by a distance of from about 5 microns to about 15 microns. 3. The method of claim 1 wherein forming the spaced-apart structures includes forming a first structure closest to one of the growth regions, and wherein the first structure is spaced apart from the one device growth region by an offset distance, and wherein the offset distance is different for a lateral LED structure than for a vertical LED structure. 4. The method of claim 1 wherein adding a first portion of gallium nitride to the growth regions includes, for an individual growth region, adding the first portion to have a generally uniform thickness across the individual device growth region, from one edge to another. 5. A method for manufacturing semiconductor devices, comprising: forming spaced-apart dummy structures at a dicing street located between neighboring device growth regions of a substrate material; epitaxially growing gallium nitride by: adding a first portion of the gallium nitride to aluminum nitride at the device growth regions; and adding a second portion of the gallium nitride to aluminum nitride at the dummy structures; forming LEDs with the gallium nitride at the device growth regions; and separating the semiconductor devices from each other at the dicing street by removing the spaced-apart structures and the underlying substrate material at the dicing street. 6. The method of claim 5 wherein adding the second portion of gallium nitride includes attracting to the spaced-apart structures gallium nitride that would otherwise nucleate at an edge of a device growth region. 7. The method of claim 5 wherein forming spaced-apart structures includes removing portions of material at the dicing street to expose the substrate material, leaving spaced-apart structures at the dicing street. 8. The method of claim 5 wherein forming spaced-apart structures includes: applying a mask to the substrate material; removing the mask from multiple device growth regions and from spaced-apart regions at the dicing street between neighboring device growth regions; and applying an aluminum nitride seed material to the device growth regions and the spaced-apart regions of the dicing street to form spaced-apart structures at the dicing street. 9. The method of claim 5 , further comprising: forming a test structure at the dicing street with at least one of the spaced-apart structures; and performing a test using the test structure before separating the LEDs. 10. The method of claim 5 wherein separating the LEDs includes sawing the underlying substrate material. 11. The method of claim 5 wherein adding the first portion of the gallium nitride to the device growth regions includes, for an individual region, adding the first portion of the gallium nitride to have a generally uniform distribution across the individual region. 12. The method of claim 11 wherein the gallium nitride at the device growth region has a first thickness away from the dicing street and a second thickness adjacent to the dicing street, and wherein the first and second thicknesses are at least approximately equal. 13. The method of claim 5 wherein forming the spaced-apart structures includes forming a first structure closest to one of the device growth regions, and wherein the first structure is spaced apart from the one device growth region by a distance of from about 5 microns to about 15 microns. 14. A method for manufacturing solid state transducers, comprising: applying a mask to a substrate material; removing the mask from multiple device growth regions and from spaced-apart regions in a dicing street between neighboring device growth regions; applying an aluminum nitride seed material to the device growth regions and the spaced-apart regions of the dicing street to form spaced-apart structures at the dicing street; epitaxially growing gallium nitride on the aluminum nitride seed material by: adding a first portion of gallium nitride to the device growth regions; and adding a second portion of gallium nitride material to the dummy structures, wherein the second portion of the gallium nitride would otherwise be disposed at the device growth regions in the absence of the spaced-apart structures; forming solid state transducers with the gallium nitride at the device growth regions; and separating the solid state transducers from each at the dicing street by removing the spaced-apart structures and the underlying substrate material at the dicing street. 15. The method of claim 14 wherein forming solid state transducers includes forming LEDs.

Assignees

Inventors

Classifications

  • Cutting or separating of wafers, substrates or parts of devices · CPC title

  • Circuits for electrically characterising or monitoring manufacturing processes, e.g. circuits in tested chips or circuits in testing wafers · CPC title

  • Interconnections for measuring or testing, e.g. probe pads · CPC title

  • characterised by the properties tested or measured, e.g. structural or electrical properties · CPC title

  • Marks applied to devices, e.g. for alignment or identification · CPC title

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What does patent US8951842B2 cover?
Semiconductor growth substrates and associated systems and methods for die singulation are disclosed. A representative method for manufacturing semiconductor devices includes forming spaced-apart structures at a dicing street located between neighboring device growth regions of a substrate material. The method can further include epitaxially growing a semiconductor material by adding a first po…
Who is the assignee on this patent?
Fang Xiaolong, Xu Lifang, Li Tingkai, and 2 more
What technology area does this patent fall under?
Primary CPC classification H10H20/01335. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue Feb 10 2015 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).