User-space emulation framework for heterogeneous soc design
US-2024004776-A1 · Jan 4, 2024 · US
US8949752B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-8949752-B2 |
| Application number | US-201314089522-A |
| Country | US |
| Kind code | B2 |
| Filing date | Nov 25, 2013 |
| Priority date | Dec 1, 2012 |
| Publication date | Feb 3, 2015 |
| Grant date | Feb 3, 2015 |
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An emulation system integrates multiple custom prototyping boards for emulating a circuit design. A first custom prototyping board including at least one FPGA and an interface connected to a first set of wires coupling to the at least one FPGA. A second custom prototyping board includes at least one second FPGA and an interface connected to a second set of wires coupling to the at least second FPGA. An adaptor board connects to the first custom prototyping board and the second custom prototyping board through the first interface and the second interface. The adapter board controls emulation of the circuit design and controls communication through the partitioned circuit using at least one of the first set of wires and at least one the second set of wires.
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What is claimed is: 1. A method for emulating a circuit design using a plurality of prototyping boards, the method comprising: connecting a first prototyping board having a set of programmable logic components to a first interface having a set of programmable logic components using a first set of wires, the first prototyping board being described by a first plurality of board description files; partitioning the circuit design according to the first plurality of board description…
Physics · mapped topic
Physics · mapped topic
Physics · mapped topic
Physics · mapped topic
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