Processor and memory communication in a stacked memory system
US-2024411709-A1 · Dec 12, 2024 · US
US8949679B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-8949679-B2 |
| Application number | US-201113086867-A |
| Country | US |
| Kind code | B2 |
| Filing date | Apr 14, 2011 |
| Priority date | Apr 6, 2011 |
| Publication date | Feb 3, 2015 |
| Grant date | Feb 3, 2015 |
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Disclosed in a method of optimizing a voltage reference signal. The method includes: assigning a first value to the voltage reference signal; executing a test pattern while using the voltage reference signal having the first value; observing whether a failure occurs in response to the executing and thereafter recording a pass/fail result; incrementing the voltage reference signal by a second value; repeating the executing, the observing, and the incrementing a plurality of times until the voltage reference signal exceeds a third value; and determining an optimized value for the voltage reference signal based on the pass/fail results obtained through the repeating the executing, the observing, and the incrementing the plurality of times.
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What is claimed is: 1. A method of optimizing a voltage reference signal, comprising: assigning a first value to the voltage reference signal; executing a test pattern while using the voltage reference signal having the first value; observing whether a failure occurs in response to the executing and thereafter recording a pass/fail result; incrementing the voltage reference signal by a second value; repeating the executing, the observing, and the incrementing a plurality o…
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