Digital phase-locked loop and related merged duty cycle calibration scheme for frequency synthesizers
US-2024171181-A1 · May 23, 2024 · US
Glitchless programmable clock shaper
US8949652B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-8949652-B2 |
| Application number | US-201113288804-A |
| Country | US |
| Kind code | B2 |
| Filing date | Nov 3, 2011 |
| Priority date | Nov 3, 2011 |
| Publication date | Feb 3, 2015 |
| Grant date | Feb 3, 2015 |
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Abstract
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In one embodiment, a microprocessor includes one or more processing cores. At least one processing core includes a clock shaping circuit that is configured to receive a clock input signal. The clock shaping circuit includes rising edge skew logic that is configured to selectively delay a rising edge of the clock input signal and falling edge skew logic that is configured to selectively delay a falling edge of the clock input signal independent of adjustment of the rising edge.
First claim
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The invention claimed is: 1. A microprocessor comprising: one or more processing cores; and a clock shaping circuit within the one or more processing cores that is configured to receive a clock input signal, the clock shaping circuit including comprising: rising edge skew logic comprising a first plurality of buffers coupled in series, wherein the rising edge skew logic is configured to selectively delay a rising edge of the clock input signal; and falling edge skew logic com…
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- H03K5/131Primary
Electricity · mapped topic
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Frequently asked questions
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- What does patent US8949652B2 cover?
- In one embodiment, a microprocessor includes one or more processing cores. At least one processing core includes a clock shaping circuit that is configured to receive a clock input signal. The clock shaping circuit includes rising edge skew logic that is configured to selectively delay a rising edge of the clock input signal and falling edge skew logic that is configured to selectively delay a …
- Who is the assignee on this patent?
- Lee Chi Keung, Nvidia Corp
- What technology area does this patent fall under?
- Primary CPC classification H03K5/131. Mapped technology areas include Electricity.
- When was this patent published?
- Publication date Tue Feb 03 2015 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
- What related patents are in patentsdb?
- We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).