Display processor and method for display processing
US-2015379971-A1 · Dec 31, 2015 · US
Idle power control in multi-display systems
US8949554B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-8949554-B2 |
| Application number | US-201113308547-A |
| Country | US |
| Kind code | B2 |
| Filing date | Dec 1, 2011 |
| Priority date | Dec 1, 2011 |
| Publication date | Feb 3, 2015 |
| Grant date | Feb 3, 2015 |
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Abstract
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A system and method for reducing power consumption of a video subsystem. A computer system includes multiple display devices supported by a graphics processor. A memory for storing video data for the multiple display devices utilizes multiple channels for higher bandwidth. A systems controller within the graphics processor determines a retraining condition, such as an idle power state, is satisfied for one or more channels of the multiple memory channels. The graphics processor divides each respective screen for the multiple display devices into multiple horizontal bars. For each one of the multiple horizontal bars, the corresponding data may be rearranged from being distributed across the multiple channels to being stored in a single one of the multiple channels. The systems controller determines a given channel is an upcoming free channel. This free channel is retrained while it is free. Retraining may include at least reducing its memory clock (MCLK) frequency.
First claim
Opening claim text (preview).
What is claimed is: 1. A processor comprising: a memory hub configured to be coupled to a memory including a plurality of memory channels; and a system manager unit (SMU); wherein in response to determining a retraining condition is satisfied for one or more channels of the plurality of memory channels, the SMU is configured to: read data from the memory that corresponds to two or more memory channels; write the data back to the memory such that the data corresponds to a si…
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Physics · mapped topic
Physics · mapped topic
- G09G5/397Primary
Physics · mapped topic
Physics · mapped topic
Cross-Sectional Technologies · mapped topic
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Frequently asked questions
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- What does patent US8949554B2 cover?
- A system and method for reducing power consumption of a video subsystem. A computer system includes multiple display devices supported by a graphics processor. A memory for storing video data for the multiple display devices utilizes multiple channels for higher bandwidth. A systems controller within the graphics processor determines a retraining condition, such as an idle power state, is satis…
- Who is the assignee on this patent?
- Sadowski Greg, Presant Stephen, Advanced Micro Devices Inc
- What technology area does this patent fall under?
- Primary CPC classification G09G5/397. Mapped technology areas include Physics.
- When was this patent published?
- Publication date Tue Feb 03 2015 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
- What related patents are in patentsdb?
- We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).