Method and apparatus to use DRAM as a cache for slow byte-addressible memory for efficient cloud applications
US-12174739-B2 · Dec 24, 2024 · US
Bypassing a cache when handling memory requests
US8949544B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-8949544-B2 |
| Application number | US-201213714559-A |
| Country | US |
| Kind code | B2 |
| Filing date | Dec 14, 2012 |
| Priority date | Nov 19, 2012 |
| Publication date | Feb 3, 2015 |
| Grant date | Feb 3, 2015 |
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Abstract
Official abstract text for this publication.
The described embodiments include a computing device that handles memory requests. In some embodiments, when a memory request is to be sent to a cache in the computing device or to be bypassed to a next lower level of a memory hierarchy in the computing device based on expected memory request resolution times, a bypass mechanism is configured to send the memory request to the cache or bypass the memory request to the next lower level of the memory hierarchy.
First claim
Opening claim text (preview).
What is claimed is: 1. A method for handling memory requests, comprising: in a bypass mechanism, performing operations for: when a memory request is to be sent to a cache or to be bypassed to a next lower level of a memory hierarchy based on expected memory request resolution times, sending the memory request to the cache or bypassing the memory request to the next lower level of the memory hierarchy. 2. The method of claim 1 , wherein the method further…
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Physics · mapped topic
- G06F12/0802Primary
Physics · mapped topic
Physics · mapped topic
Physics · mapped topic
- G06F12/0897Primary
Physics · mapped topic
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- What does patent US8949544B2 cover?
- The described embodiments include a computing device that handles memory requests. In some embodiments, when a memory request is to be sent to a cache in the computing device or to be bypassed to a next lower level of a memory hierarchy in the computing device based on expected memory request resolution times, a bypass mechanism is configured to send the memory request to the cache or bypass th…
- Who is the assignee on this patent?
- Advanced Micro Devices Inc, Advanced Micro Devices Inc
- What technology area does this patent fall under?
- Primary CPC classification G06F12/0802. Mapped technology areas include Physics.
- When was this patent published?
- Publication date Tue Feb 03 2015 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
- What related patents are in patentsdb?
- We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).