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US-2017068536-A1 · Mar 9, 2017 · US
Conditional load and store in a shared memory
US8949539B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-8949539-B2 |
| Application number | US-69779910-A |
| Country | US |
| Kind code | B2 |
| Filing date | Feb 1, 2010 |
| Priority date | Nov 13, 2009 |
| Publication date | Feb 3, 2015 |
| Grant date | Feb 3, 2015 |
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Abstract
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A method, system and computer program product for implementing load-reserve and store-conditional instructions in a multi-processor computing system. The computing system includes a multitude of processor units and a shared memory cache, and each of the processor units has access to the memory cache. In one embodiment, the method comprises providing the memory cache with a series of reservation registers, and storing in these registers addresses reserved in the memory cache for the processor units as a result of issuing load-reserve requests. In this embodiment, when one of the processor units makes a request to store data in the memory cache using a store-conditional request, the reservation registers are checked to determine if an address in the memory cache is reserved for that processor unit. If an address in the memory cache is reserved for that processor, the data are stored at this address.
First claim
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The invention claimed is: 1. A method of implementing conditional memory reservations in a multi-processor computing system to maintain memory consistency in a shared memory, the computing system including a multitude of processor units and a shared memory, wherein all of the processor units have access to the shared memory, and the processor units make load-reserve requests to reserve an address in the shared memory and make store-conditional requests to store data to the reserved…
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- G06F15/17381Primary
Physics · mapped topic
Physics · mapped topic
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Frequently asked questions
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- What does patent US8949539B2 cover?
- A method, system and computer program product for implementing load-reserve and store-conditional instructions in a multi-processor computing system. The computing system includes a multitude of processor units and a shared memory cache, and each of the processor units has access to the memory cache. In one embodiment, the method comprises providing the memory cache with a series of reservation…
- Who is the assignee on this patent?
- Blumrich Matthias A, Ohmacht Martin, IBM
- What technology area does this patent fall under?
- Primary CPC classification G06F15/17381. Mapped technology areas include Physics.
- When was this patent published?
- Publication date Tue Feb 03 2015 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
- What related patents are in patentsdb?
- We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).