Storage control apparatus and method for detecting write completion of data

Patent metadata

Field	Value
Publication number	US-8949537-B2
Application number	US-201314241841-A
Country	US
Kind code	B2
Filing date	Feb 25, 2013
Priority date	Feb 25, 2013
Publication date	Feb 3, 2015
Grant date	Feb 3, 2015

Abstract

A processor transmits, to a communication control module, at least one write request packet with which at least one data block element configuring a data block is respectively associated, and updates a first counter to a value corresponding to the number of the transmitted write request packets. The communication control module writes a data block element associated with the write request packet to a cache memory, updates a third counter to a value corresponding to the number of the transmitted data block elements, and reflects the third counter to a second counter. The processor determines that the data block is written to the cache memory when the second counter reaches the first counter after all write request packets are transmitted.

First claim

The invention claimed is:

1. A storage control apparatus comprising:
a first and a second processors;
a first and a second cache memories;
a local memory;
a processor interface module that is an interface to the first processor; and
a cache interface module that is an interface to the first cache memory,
wherein
the local memory has a first table including at least one first counter and a second table including at least one second counter;
the processor interface mod…

Assignees

• Hitachi Ltd

Inventors

• Moritoki Naoki
• Asakawa Shohei
• Yamauchi Takeshi
• Shimotaya Suguru

Classifications

• G06F12/0868 Primary

  Physics · mapped topic

• G06F12/0813 Primary

  Physics · mapped topic

• G06F12/0804

  Physics · mapped topic