Heterogeneous memory systems, and related methods and computer-readable media for supporting heterogeneous memory access requests in processor-based systems
US-9224452-B2 · Dec 29, 2015 · US
Memory devices and memory control methods with ISP code
US8949504B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-8949504-B2 |
| Application number | US-201213621493-A |
| Country | US |
| Kind code | B2 |
| Filing date | Sep 17, 2012 |
| Priority date | Jul 5, 2012 |
| Publication date | Feb 3, 2015 |
| Grant date | Feb 3, 2015 |
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Abstract
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A memory device is provided, including a first memory die, a second memory die and a controller. The first memory die has a first system block. The second memory die has a second system block. The controller is coupled to the first and second memory dies through a chip enable lane in order to write the same in-system programming codes (ISP codes) to the first and second system blocks, in which, when the memory device is turned on, the controller reads the ISP code from the first system block or the second system block.
First claim
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What is claimed is: 1. A memory device, comprising a first memory die, having a first system block; a second memory die, having a second system block; and a controller, coupled to the first and second memory dies through a chip enable lane in order to write the same in-system programming codes (ISP codes) to the first and second system blocks, wherein, when the memory device is turned on, the controller reads the ISP code from the first system block or the second system block.…
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- G06F13/1694Primary
Physics · mapped topic
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- What does patent US8949504B2 cover?
- A memory device is provided, including a first memory die, a second memory die and a controller. The first memory die has a first system block. The second memory die has a second system block. The controller is coupled to the first and second memory dies through a chip enable lane in order to write the same in-system programming codes (ISP codes) to the first and second system blocks, in which,…
- Who is the assignee on this patent?
- Yan Wei-Lun, Lo Chun-Yi, Silicon Motion Inc
- What technology area does this patent fall under?
- Primary CPC classification G06F13/1694. Mapped technology areas include Physics.
- When was this patent published?
- Publication date Tue Feb 03 2015 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
- What related patents are in patentsdb?
- We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).