Non-blocking processor bus bridge for network processors or the like

Patent metadata

Field	Value
Publication number	US-8949500-B2
Application number	US-201213409432-A
Country	US
Kind code	B2
Filing date	Mar 1, 2012
Priority date	Aug 8, 2011
Publication date	Feb 3, 2015
Grant date	Feb 3, 2015

Abstract

Described embodiments provide a system having a bridge for connecting two different processor buses. The bridge receives a request from a first bus, the request having an identification field having a value. The request is then entered into one of a plurality of buffers having requests therein with the same identification field values. Which buffer receives the request may be based on a variety of techniques, such as random, least recently used, most full, prioritized, or sequential. Next, the buffered request is transmitted over a second bus. A response to the request is eventually received from the second bus, the response is transmitted over the first bus, and the request is then removed from the buffer. By entering the received request to the buffer with request with the same identification value, there is a reduced possibility of head-of-line request blocking when compared to a single buffer implementation.

First claim

The invention claimed is:

1. In a bridge coupling between a first bus and a second bus, a method for communicating between the first and second buses comprising:
A) receiving from the first bus a candidate request having an identification field, the identification field having a value;
B) selecting one of a plurality of buffers based on the identification field value;
C) entering the candidate request into the selected buffer;
D) reading a request from a specified one of the…

Assignees

• Byrne Richard J
• Masters David S
• Lsi Corp

Inventors

• Byrne Richard J
• Masters David S

Classifications

• G06F13/362 Primary

  Physics · mapped topic