Information processing system and information processing method
US-2024380982-A1 · Nov 14, 2024 · US
US8949490B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-8949490-B2 |
| Application number | US-201313768493-A |
| Country | US |
| Kind code | B2 |
| Filing date | Feb 15, 2013 |
| Priority date | Mar 8, 2012 |
| Publication date | Feb 3, 2015 |
| Grant date | Feb 3, 2015 |
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Disclosed herein is a data reception circuit including a clock generation block configured to divide a first clock based on clock information, the first clock being the clock of a transmission stream targeted to transmit video data between apparatuses, the clock information indicating a cyclical relationship between the first clock and a second clock serving as the clock of predetermined data, the clock generation block further outputting the divided clock as the second clock.
Opening claim text (preview).
What is claimed is: 1. A data reception circuit comprising, a clock generation block configured to divide a first clock based on clock information, said first clock being the clock of a transmission stream targeted to transmit video data between apparatuses, said clock information indicating a cyclical relationship between said first clock and a second clock serving as the clock of predetermined data, said clock generation block further outputting the divided clock as said second…
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