Acquiring graphical operating system post-failure screen

US8949404B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-8949404-B2
Application numberUS-13576105-A
CountryUS
Kind codeB2
Filing dateMay 24, 2005
Priority dateMay 24, 2005
Publication dateFeb 3, 2015
Grant dateFeb 3, 2015

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  2. Abstract

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  5. First independent claim

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Abstract

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Systems, methodologies, and media associated with acquiring a graphics mode post-failure screen provided by a graphical operating system running on a self-reset capable computer are described. One exemplary method embodiment may be performable in a management processor (e.g., ASIC, FPGA) that is configured to be operably connected to a computer (e.g., server) that is configured to provide a graphical post-failure screen and to self-reset upon entering a failure state. The exemplary method embodiment may include receiving a stream of video data from the computer and making it available to a downstream component like a remote console application. The exemplary method may also include performing a screen refresh after detecting the failure state in the computer. The exemplary method may also include selectively storing the graphical post-failure screen in a memory associated with the management processor.

First claim

Opening claim text (preview).

What is claimed is: 1. A system, comprising: a compression logic configured to receive a digital video stream from a video adapter associated with a computer with a display, to compress the digital video stream into a compressed digital video data, and to make the compressed digital video data available to a downstream component; a control logic configured to detect that the computer has entered a failure state due to an unrecoverable error that will cause the computer to automa…

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What does patent US8949404B2 cover?
Systems, methodologies, and media associated with acquiring a graphics mode post-failure screen provided by a graphical operating system running on a self-reset capable computer are described. One exemplary method embodiment may be performable in a management processor (e.g., ASIC, FPGA) that is configured to be operably connected to a computer (e.g., server) that is configured to provide a gra…
Who is the assignee on this patent?
Luciani Jr Luis E, Dykes Don A, Hewlett Packard Development Co
What technology area does this patent fall under?
Primary CPC classification G06F11/1441. Mapped technology areas include Physics.
When was this patent published?
Publication date Tue Feb 03 2015 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).