Automatic compilation method and framework for generating a layout of integrated memory-compute circuit
US-2024403527-A1 · Dec 5, 2024 · US
US8949083B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-8949083-B2 |
| Application number | US-201113194644-A |
| Country | US |
| Kind code | B2 |
| Filing date | Jul 29, 2011 |
| Priority date | Jul 29, 2011 |
| Publication date | Feb 3, 2015 |
| Grant date | Feb 3, 2015 |
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A method for modeling a transistor includes providing a transistor model having at least a source node, a drain node, and a gate node, simulating operation of a device using the transistor model in a computing apparatus, and generating an offset voltage at the gate node depending on a magnitude of a current passing through the device.
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We claim: 1. A method for modeling a transistor, comprising: providing a transistor model for the transistor having at least a source node, a drain node, a gate node, and a gate transconductance node coupled to the gate node; simulating operation of a device including the transistor using the transistor model in a computing apparatus; and during the simulating, generating an offset voltage at the gate transconductance node depending on a magnitude of a current passing through…
Physics · mapped topic
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