Data switch

Patent metadata

Field	Value
Publication number	US-8948192-B2
Application number	US-201213408634-A
Country	US
Kind code	B2
Filing date	Feb 29, 2012
Priority date	Oct 16, 2007
Publication date	Feb 3, 2015
Grant date	Feb 3, 2015

Abstract

A data switch for an integrated circuit comprising at least one link for receiving input data packets from an independently modulated spread spectrum clock (SSC) enabled source having predetermined spread spectrum link clock frequency characteristics, and at least one output for transmitting the data packets after passage through the switch, the switch further comprising at least one receive buffer having a link side and a core side for receiving the SSC modulated input data packets from the link, at least one transmit buffer and a core clock, wherein the core clock operates at a given frequency between predetermined error limits determined by oscillation accuracy alone and is not SSC-enabled, the core clock frequency being set at a level at least as high as the highest link clock frequency such that the receive buffer cannot be filled faster from its link side than it can be emptied from its core side.

First claim

The invention claimed is:

1. A switch comprising:
a core clock that is not spread spectrum clock (SSC) enabled, the core clock generating a core clock signal;
a link to receive input, the link comprising one or more discrete conductors along which serial data in a plurality of lanes within the link is delivered into and through the switch;
a transmitting output, connected to a switch core, to deliver deserialized data;
means to deserialize data received from the link;
elas…

Assignees

• Naven Finbar
• Drewry John Roger
• Micron Technology Inc

Inventors

• Naven Finbar
• Drewry John Roger

Classifications

• H04L49/90

  Electricity · mapped topic

• H04J3/0685 Primary

  Electricity · mapped topic

• H04L49/3018

  Electricity · mapped topic

• H04L49/3027

  Electricity · mapped topic

• H04L2012/5674

  Electricity · mapped topic