Page buffer performing memory operation
US-2024274171-A1 · Aug 15, 2024 · US
US8947951B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-8947951-B2 |
| Application number | US-201313836902-A |
| Country | US |
| Kind code | B2 |
| Filing date | Mar 15, 2013 |
| Priority date | Jun 22, 2012 |
| Publication date | Feb 3, 2015 |
| Grant date | Feb 3, 2015 |
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A semiconductor memory device includes at least one memory cell connected to an internal voltage line that receives a cell power supply voltage and a write assist circuit connected to the internal voltage line. The write assist circuit lowers a level of the cell power supply voltage to a target level during a first period of a write operation on the memory cell and maintains the level of the cell power supply voltage at the target level during a second period of the write operation based on a write assist control signal. The second period succeeds the first period.
Opening claim text (preview).
What is claimed is: 1. A semiconductor memory device comprising: at least one memory cell connected to an internal voltage line that receives a cell power supply voltage; a write assist circuit connected to the internal voltage line, the write assist circuit configured to lower a level of the cell power supply voltage to a target level during a first period of a write operation on the memory cell and configured to maintain the level of the cell power supply voltage at the target…
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