Semiconductor structure with flush shallow trench isolation and gate oxide and method of manufacturing the same
US-2024395883-A1 · Nov 28, 2024 · US
Semiconductor device
US8947950B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-8947950-B2 |
| Application number | US-201313770150-A |
| Country | US |
| Kind code | B2 |
| Filing date | Feb 19, 2013 |
| Priority date | Apr 23, 2012 |
| Publication date | Feb 3, 2015 |
| Grant date | Feb 3, 2015 |
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Abstract
Official abstract text for this publication.
A semiconductor memory device includes a bit line connected to a memory cell; an input/output line configured to input a data signal to the memory cell during a writing operation and to output a data signal stored in the memory cell during a reading operation; and a column select transistor including a first source/drain connected to the bit line and a second source/drain connected to the input/output line, wherein a resistance of the first source/drain is smaller than a resistance of the second source/drain.
First claim
Opening claim text (preview).
What is claimed is: 1. A semiconductor memory device comprising: a bit line connected to a memory cell; an input/output line configured to input a data signal to the memory cell during a writing operation and to output a data signal stored in the memory cell during a reading operation; and a column select transistor comprising a first source/drain connected to the bit line and a second source/drain connected to the input/output line, wherein a resistance of the first source/…
Assignees
Inventors
Classifications
- H10D30/65Primary
Electricity · mapped topic
- G11C11/4094Primary
Physics · mapped topic
Physics · mapped topic
Physics · mapped topic
- H01L29/7816Primary
Electricity · mapped topic
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Frequently asked questions
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- What does patent US8947950B2 cover?
- A semiconductor memory device includes a bit line connected to a memory cell; an input/output line configured to input a data signal to the memory cell during a writing operation and to output a data signal stored in the memory cell during a reading operation; and a column select transistor including a first source/drain connected to the bit line and a second source/drain connected to the input…
- Who is the assignee on this patent?
- Samsung Electronics Co Ltd
- What technology area does this patent fall under?
- Primary CPC classification H10D30/65. Mapped technology areas include Electricity.
- When was this patent published?
- Publication date Tue Feb 03 2015 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
- What related patents are in patentsdb?
- We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).