Neural network computation circuit, control circuit therefor, and control method therefor
US-2024411520-A1 · Dec 12, 2024 · US
Thyristor memory cell integrated circuit
US8947925B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-8947925-B2 |
| Application number | US-201313951578-A |
| Country | US |
| Kind code | B2 |
| Filing date | Jul 26, 2013 |
| Priority date | Aug 17, 2012 |
| Publication date | Feb 3, 2015 |
| Grant date | Feb 3, 2015 |
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Abstract
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A semiconductor memory device including an array of memory cells (MC) formed on a substrate each realized from a load element and thyristor that define a switchable current path whose state represents a volatile bit value stored by the MC. At least one word line corresponding to a respective row of the array is formed on the substrate and coupled to MC current paths for the corresponding row. Bit lines corresponding to respective columns of the array are formed on the substrate and can be coupled to a modulation doped QW interface of the MC thyristors for the corresponding column. Circuitry is configured to apply an electrical signal to the word line(s) in order to generate current that programs phase change material of the MC load elements into one of a high or low resistive state according to state of the current path of the MCs for non-volatile backup purposes.
First claim
Opening claim text (preview).
What is claimed is: 1. A semiconductor memory device comprising: an array of memory cells formed on a substrate, each given memory cell including a resistive load element and a thyristor device that define a switchable current path through the resistive load element and the thyristor device of the given memory cell, wherein the resistive load element is realized from a phase change material that can be selectively programmed into one of a high resistive state and a low resistive s…
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- G11C13/0004Primary
Physics · mapped topic
Physics · mapped topic
Physics · mapped topic
Physics · mapped topic
Physics · mapped topic
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- What does patent US8947925B2 cover?
- A semiconductor memory device including an array of memory cells (MC) formed on a substrate each realized from a load element and thyristor that define a switchable current path whose state represents a volatile bit value stored by the MC. At least one word line corresponding to a respective row of the array is formed on the substrate and coupled to MC current paths for the corresponding row. B…
- Who is the assignee on this patent?
- Taylor Geoff W, Univ Connecticut, Opel Solar Inc
- What technology area does this patent fall under?
- Primary CPC classification G11C13/0004. Mapped technology areas include Physics.
- When was this patent published?
- Publication date Tue Feb 03 2015 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
- What related patents are in patentsdb?
- We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).