Apparatus and methods for altering the timing of a clock signal
US-9225319-B2 · Dec 29, 2015 · US
US8947839B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-8947839-B2 |
| Application number | US-51244109-A |
| Country | US |
| Kind code | B2 |
| Filing date | Jul 30, 2009 |
| Priority date | Jul 30, 2009 |
| Publication date | Feb 3, 2015 |
| Grant date | Feb 3, 2015 |
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Enhanced electrostatic discharge (“ESD”) protection for an integrated circuit is described. An embodiment relates generally to a circuit for protection against ESD. The circuit has an input/output node and a driver. The driver has a first transistor and a second transistor. A first source/drain node of the first transistor is coupled to the input/output node. A second source/drain node of the first transistor forms a first interior node capable of accumulating charge when electrically floating. A first current flow control circuit is coupled to a discharge node and the second source/drain node of the first transistor. The first current flow control circuit is electrically oriented in a bias direction for allowing accumulated charge to discharge from the first interior node via the first current flow control circuit to the discharge node.
Opening claim text (preview).
What is claimed is: 1. A circuit for protection against electrostatic discharge, comprising: an input/output node and a driver, wherein the driver includes a first transistor and a second transistor of a same polarity coupled to one another in source-drain series at a first interior node of the driver; a first source/drain node of the first transistor coupled to the input/output node; a second source/drain node of the first transistor of the first interior node of the driver c…
Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
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