Core voltage reset systems and methods with wide noise margin

Patent metadata

Field	Value
Publication number	US-8947137-B2
Application number	US-201213730668-A
Country	US
Kind code	B2
Filing date	Dec 28, 2012
Priority date	Sep 5, 2012
Publication date	Feb 3, 2015
Grant date	Feb 3, 2015

Abstract

Presented systems and methods facilitate efficient reset operation. In one embodiment, a system comprises a core domain portion an I/O domain portion and a core reset I/O by-pass component. The core domain portion is configured to operate at a nominal core domain voltage level. The I/O domain portion configured to operate at a nominal I/O domain voltage level. The core reset I/O by-pass component configured to forward a reset indication to the core domain independent of the I/O domain. In one exemplary implementation the core reset I/O by-pass component is operable to receive an input reset indication at a high domain voltage level and to convert the input reset indication to a core reset signal that is less than or substantially equal to the nominal core domain voltage, wherein the high domain is voltage higher than the core domain voltage level.

First claim

What is claimed is:

1. A system comprising:
a core domain portion configured to operate at a nominal core domain voltage level;
an I/O domain portion configured to operate at a nominal I/O domain voltage level that is different from said nominal core domain voltage level; and
a core reset I/O by-pass component configured to forward a reset indication to the core domain portion independent of the I/O domain portion.

2. The system as described in claim 1 wherein the core reset I/O by-pass component is operable to receive an input reset indication at a high domain voltage level and to convert the input reset indication to a core reset signal that is less than or substantially equal to the nominal core domain voltage level, wherein the high domain voltage level is greater than the nominal core domain voltage level.

3. The system as described in claim 2 , wherein the core reset I/O by-pass component comprises a reset protection circuit and a level restoration circuit, wherein the level restoration circuit is configured to pull the core reset signal up to the nominal core domain voltage level.

4. The system as described in claim 3 , wherein the reset protection circuit comprises a native thick oxide N channel transistor connected in series with a thin channel transistor, wherein both the native thick oxide N channel transistor and the thin channel transistor have a gate coupled to the core domain voltage level; and wherein the native thick oxide N channel transistor has a threshold voltage substantially equal to or less than zero.

5. The system as described in claim 2 , wherein the high domain voltage level is equal to the nominal I/O domain voltage level.

6. The system as described in claim 2 , wherein the core domain portion is operable to receive the core reset signal before an I/O domain rail associated with the I/O domain portion is powered up.

7. The system as described in claim 1 , wherein the core reset I/O by-pass component further comprises a noise margin amplification circuit that comprises a half-Schmitt trigger circuit operable to increase the Voltage-In-Low (VIL) of the core domain portion in response to a converted reset signal.

8. A method comprising:
receiving a reset indication;
performing a core reset I/O by-pass process, wherein the core reset I/O by-pass process comprises forwarding a core reset signal to a core domain in response to the reset indication and independent of an I/O domain, wherein said core domain and said I/O domain operate in different voltage levels; and
resetting the core domain.

9. The method as described in claim 8 , wherein the performing a core reset I/O by-pass process includes increasing a noise margin.

10. The method as described in claim 9 , wherein the performing a core reset I/O by-pass process includes converting the reset indication to a converted reset signal that is substantially equal to or less than a core domain voltage and pulling the converted reset signal to the core domain voltage.

11. The method as described in claim 10 , wherein the reset indication is substantially equal to an I/O domain voltage when received, and wherein the core reset signal is forwarded by the core reset I/O by-pass process substantially equal to or less than the core domain voltage.

12. The method as described in claim 11 , wherein the converted reset signal is forwarded to the core domain before the I/O domain is powered up.

13. The method as described in claim 9 wherein increasing the noise margin includes increasing Voltage-Input-Low (VIL).

14. A system comprising:
a core domain circuit configured to operate at a nominal core domain voltage level;
an I/O domain circuit configured to operate at a nominal I/O domain voltage level, wherein the I/O domain circuit comprises an I/O domain rail; and
a core reset I/O by-pass circuit configured to forward a reset indication to the core domain circuit independent of the I/O domain circuit,
wherein the core domain circuit is configured to receive the reset indication before the I/O domain rail is powered up.

15. The system as described in claim 14 , wherein the reset indication comprises an input reset signal, wherein the core reset I/O by-pass circuit is operable to receive the input reset signal at a high domain voltage level and to convert the input reset signal to a core reset signal that is less than or substantially equal to the nominal core domain voltage level, wherein the high domain voltage level is greater than the nominal core domain voltage level.

16. The system as described in claim 15 , wherein the core reset I/O by-pass circuit comprises a reset protection circuit and a level restoration circuit, wherein the level restoration circuit is operable to pull the core reset signal up to the nominal core domain voltage level.

17. The system as described in claim 16 , wherein the reset protection circuit comprises a native thick oxide N channel transistor connected in series with a thin layer transistor, wherein both the native thick oxide N channel transistor and the thin layer transistor have a gate coupled to the core domain voltage level; and wherein the native thick oxide N channel transistor has a threshold voltage substantially equal to or less than zero.

18. The system as described in claim 15 , wherein the high domain voltage level is equal to the nominal I/O domain voltage level.

19. The system as described in claim 15 , wherein the core reset I/O by-pass circuit further comprises a noise margin amplification circuit configured to increase the Voltage-In-Low (VIL) of the core domain circuit in response to the core reset signal.

20. The system as described in claim 19 , wherein the noise margin amplification circuit comprises a half-Schmitt trigger circuit.

Assignees

• Nvidia Corp

Inventors

• Li Alan

Classifications

• H10W90/00

  Package configurations · CPC title

• H03K19/018507

  Interface arrangements · CPC title

• H03K19/017509 Primary

  Interface arrangements · CPC title

• H03L9/00 Primary

  Automatic control not provided for in other groups of this subclass · CPC title

• H01L25/03

  Electricity · mapped topic