Data bus signal conditioner and level shifter
US-2024396554-A1 · Nov 28, 2024 · US
US8947124B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-8947124-B2 |
| Application number | US-201414178477-A |
| Country | US |
| Kind code | B2 |
| Filing date | Feb 12, 2014 |
| Priority date | Feb 15, 2013 |
| Publication date | Feb 3, 2015 |
| Grant date | Feb 3, 2015 |
A practical reading order for non-experts. Skip the full description unless you need deep technical detail.
What the patent document calls the invention.
A short plain-language summary of the technical disclosure.
Who owns or filed the patent and who is credited as inventor.
Filing, priority, publication, and grant dates set the timeline.
The legal scope of protection — read this for what is actually claimed.
Technology tags used to group this patent with similar filings.
Prior art links and similar publications in this corpus.
Official abstract text for this publication.
An integrated circuit device comprising first circuitry including first logic devices and a clock tree for distributing a clock signal to the first logic devices and second circuitry comprising second logic devices, a first clock gater and a second clock gater. The first and second clock gaters comprise a programmable delay circuit.
Opening claim text (preview).
What is claimed is: 1. An integrated circuit device comprising: first circuitry comprising first logic devices and a clock tree configured to distribute a clock signal to the first logic devices; and second circuitry comprising second logic devices, a first clock gater and a second clock gater, wherein each of the first and second clock gaters comprises a programmable delay circuit including a plurality of delay elements, each element configured to impose a different amount of…
Electricity · mapped topic
Related publications grouped by family.
Free tools are coming soon. Tell us what you want to track and we'll notify you.
Answers are generated from the same data shown on this page.