Wafer level fan-out package with a fiducial die

Patent metadata

Field	Value
Publication number	US-8946883-B2
Application number	US-201313963384-A
Country	US
Kind code	B2
Filing date	Aug 9, 2013
Priority date	Sep 20, 2012
Publication date	Feb 3, 2015
Grant date	Feb 3, 2015

Abstract

A wafer level fan-out package with a fiducial die is disclosed and may include a semiconductor die and a transparent fiducial die both encapsulated in a molding compound resin, passivation layers on an upper surface and a lower surface of the molding compound resin except where redistribution layers are formed on upper and lower surfaces of the molding compound resin, and a metal pattern on a lower surface of the transparent fiducial die that is visible through an exposed upper surface of the transparent fiducial die. The pattern may comprise a standard coordinate for forming a through mold via utilizing laser drilling.

First claim

What is claimed is:

1. A semiconductor device comprising:
a semiconductor die and a transparent fiducial die both encapsulated in a molding compound resin;
an upper passivation layer on an upper surface of the molding compound resin except where an upper redistribution layer is formed on the upper surface of the molding compound resin;
a lower passivation layer on a lower surface of the molding compound resin except where a lower redistribution layer is formed on the lower surface of the molding compound resin;
a metal pattern on a lower surface of the transparent fiducial die that is visible through an exposed upper surface of the transparent fiducial die; and
a through mold via formed in the mold compound resin utilizing laser drilling recognizing the metal pattern as a standard coordinate, wherein said through mold via extends from the upper surface to the lower surface of the molding compound resin for electrically coupling the upper redistribution layer to the lower redistribution layer.

2. The semiconductor device according to claim 1 , wherein the pattern is embedded in the lower surface of the fiducial die.

3. The semiconductor device according to claim 1 , wherein the pattern is deposited on the lower surface of the fiducial die.

4. The semiconductor device according to claim 1 , wherein the lower redistribution layer is electrically coupled to a bonding pad on the semiconductor die.

5. The semiconductor device according to claim 1 , wherein an input/output terminal is formed on the upper redistribution layer.

6. The semiconductor device according to claim 5 , wherein the input/output terminal comprises a solder bump.

7. The semiconductor device according to claim 1 , wherein the transparent fiducial die is thicker than the semiconductor die.

8. The device according to claim 1 , wherein the transparent fiducial die comprises a glass material.

9. The semiconductor device according to claim 1 , wherein the pattern on the lower surface of the transparent fiducial die comprises the same material as the lower redistribution layer.

10. The semiconductor device according to claim 1 , wherein the formed through mold via comprises a conductive metal material.

11. A method for a semiconductor device, the method comprising:
encapsulating a semiconductor die and a transparent fiducial die in a molding compound resin;
forming passivation layers on a portion of an upper surface and a portion of a lower surface of the molding compound resin;
forming a redistribution layer on an upper surface of the molding compound resin;
forming a redistribution layer on a lower surface of the molding compound concurrently with a metal pattern on a lower surface of the transparent fiducial die, wherein the pattern is visible through an exposed upper surface of the transparent fiducial die; and
forming a through mold via utilizing laser drilling wherein the metal pattern formed on the lower surface of the transparent fiducial die comprises a standard coordinate for the laser drilling and wherein the through mold via extends from the upper surface to the lower surface of the molding compound resin.

12. The method according to claim 11 , comprising embedding the pattern in the lower surface of the fiducial die.

13. The method according to claim 11 , comprising depositing the pattern on the lower surface of the fiducial die.

14. The method according to claim 11 , wherein the redistribution layer on the lower surface of the molding compound resin is electrically coupled to a bonding pad on the semiconductor die.

15. The method according to claim 11 , wherein an input/output terminal is formed on the redistribution layer on the upper surface of the molding compound resin.

16. The method according to claim 15 , wherein the input/output terminal comprises a solder bump.

17. The method according to claim 11 , wherein the transparent fiducial die is thicker than the semiconductor die.

18. The method according to claim 11 , wherein the transparent fiducial die comprises a glass material.

19. The method according to claim 11 , comprising filling a hole resulting from the laser drilling with a conductive metal material to form the formed through mold via.

20. A semiconductor device comprising:
a semiconductor die and a transparent fiducial die both encapsulated in a molding compound resin;
passivation layers on an upper surface and a lower surface of the molding compound resin except where redistribution layers are formed on upper and lower surfaces of the molding compound resin;
a metal pattern on a lower surface of the transparent fiducial die that is visible through an exposed upper surface of the transparent fiducial die; and
a through mold via formed in the molding compound resin utilizing laser drilling recognizing the metal pattern as a standard coordinate, wherein said through mold via extends from the upper surface to the lower surface of the molding compound resin and is filled with metal for electrically coupling a redistribution layer on the upper surface of the molding compound resin to a redistribution layer on the bottom surface of the molding compound resin.

Assignees

• Amkor Technology Inc

Inventors

• Kim Sung Kyu
• Kim Jin Young
• Kim Yoon Joo
• Kim Jin Han
• Lee Seung Jae
• Cha Se Woong
• Bae Jae Hun
• Kim Dong Jin
• Ki Won Myoung

Classifications

• H10W74/111

  the semiconductor body being completely enclosed · CPC title

• H10W74/019

  using temporary auxiliary substrates (H10W74/017 takes precedence) · CPC title

• H10W74/00

  Encapsulations, e.g. protective coatings · CPC title

• H10W72/9413

  on encapsulations · CPC title

• H10W72/241

  Dispositions, e.g. layouts · CPC title