Method of eDRAM DT strap formation in FinFET device structure

Patent metadata

Field	Value
Publication number	US-8946802-B2
Application number	US-201213570379-A
Country	US
Kind code	B2
Filing date	Aug 9, 2012
Priority date	Jul 24, 2012
Publication date	Feb 3, 2015
Grant date	Feb 3, 2015

Abstract

The specification and drawings present a new method, device and computer/software related product (e.g., a computer readable memory) are presented for realizing eDRAM strap formation in Fin FET device structures. Semiconductor on insulator (SOI) substrate comprising at least an insulator layer between a first semiconductor layer and a second semiconductor layer is provided. The (metal) strap formation is accomplished by depositing conductive layer on fins portion of the second semiconductor layer (Si) and a semiconductor material (polysilicon) in each DT capacitor extending to the second semiconductor layer. The metal strap is sealed by a nitride spacer to prevent the shorts between PWL and DT capacitors.

First claim

The invention claimed is:

1. A device for an embedded dynamic random access memory (eDRAM) deep trench (DT) strap formation in a fin-shaped field effect transistor (FinFET) device structure, the device comprising:
a semiconductor on insulator (SOI) substrate comprising at least an insulator layer between a first semiconductor layer and a second semiconductor layer;
a plurality of deep trench (DT) capacitors in the first semiconductor layer of the SOI substrate for the eDRAM, wit…

Assignees

• Basker Veeraraghavan S
• Kanakasabapathy Sivananda
• Yamashita Tenko
• Yeb Chun-Chen
• IBM

Inventors

• Basker Veeraraghavan S
• Kanakasabapathy Sivananda
• Yamashita Tenko
• Yeb Chun-Chen

Classifications

• H10D86/215

  Electricity · mapped topic

• H10D86/011 Primary

  Electricity · mapped topic

• H10B12/36

  Electricity · mapped topic

• H10B12/0385 Primary

  Electricity · mapped topic

• H10B12/056

  Electricity · mapped topic