Semiconductor device and method of manufacturing the same

US8946790B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-8946790-B2
Application numberUS-201213488791-A
CountryUS
Kind codeB2
Filing dateJun 5, 2012
Priority dateJun 10, 2011
Publication dateFeb 3, 2015
Grant dateFeb 3, 2015

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  1. Title

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  2. Abstract

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  4. Key dates

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  5. First independent claim

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Abstract

Official abstract text for this publication.

A transistor which includes an oxide semiconductor and is capable of high-speed operation and a method of manufacturing the transistor. In addition, a highly reliable semiconductor device including the transistor and a method of manufacturing the semiconductor device. The semiconductor device includes an oxide semiconductor layer including a channel formation region, and a source and drain regions which are provided so that the channel formation region is interposed therebetween and have lower resistance than the channel formation region. The channel formation region and the source and drain regions each include a crystalline region.

First claim

Opening claim text (preview).

What is claimed is: 1. A semiconductor device comprising: a c-axis aligned crystalline oxide semiconductor layer including indium, gallium, and zinc, the crystalline oxide semiconductor layer comprising a source region, a drain region, and a channel formation region; a gate insulating layer over the channel formation region; and a gate electrode over the channel formation region with the gate insulating layer positioned therebetween, wherein the source region and the drain region are crystalline regions containing nitrogen. 2. The semiconductor device according to claim 1 , wherein the source region and the drain region have higher crystallinity than the channel formation region. 3. The semiconductor device according to claim 1 , wherein the gate electrode contains nitrogen. 4. The semiconductor device according to claim 1 , wherein the gate insulating layer does not overlap with the source region or the drain region. 5. The semiconductor device according to claim 1 , wherein the source region and the drain region have higher carrier density than the channel formation region. 6. The semiconductor device according to claim 1 , wherein the gate insulating layer includes hafnium oxide, yttrium oxide, hafnium silicate, hafnium silicate to which nitrogen is added, hafnium aluminate, or lanthanum oxide. 7. A semiconductor device comprising: a c-axis aligned crystalline oxide semiconductor layer including indium, gallium, and zinc, the crystalline oxide semiconductor layer comprising a source region, a drain region, and a channel formation region; a gate insulating layer over the channel formation region; a gate electrode over the channel formation region with the gate insulating layer positioned therebetween; an insulating layer having openings and positioned over the crystalline oxide semiconductor layer and the gate electrode; and a source electrode and a drain electrode respectively in contact with the source region and the drain region through the openings in the insulating layer, wherein the source region and the drain region are crystalline regions containing nitrogen. 8. The semiconductor device according to claim 7 , wherein the source region and the drain region have higher crystallinity than the channel formation region. 9. The semiconductor device according to claim 7 , wherein the gate electrode contains nitrogen. 10. The semiconductor device according to claim 7 , wherein the gate insulating layer does not overlap with the source region or the drain region. 11. The semiconductor device according to claim 7 , wherein the source region and the drain region have higher carrier density than the channel formation region. 12. The semiconductor device according to claim 7 , wherein the gate insulating layer includes hafnium oxide, yttrium oxide, hafnium silicate, hafnium silicate to which nitrogen is added, hafnium aluminate, or lanthanum oxide.

Assignees

Inventors

Classifications

  • being oxide semiconductor materials (Group IIB-VIA semiconductor materials H10P14/3424) · CPC title

  • Oxides · CPC title

  • characterised by treatments done after the formation of the materials · CPC title

  • of semiconductor materials · CPC title

  • using physical deposition, e.g. vacuum deposition or sputtering · CPC title

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Frequently asked questions

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What does patent US8946790B2 cover?
A transistor which includes an oxide semiconductor and is capable of high-speed operation and a method of manufacturing the transistor. In addition, a highly reliable semiconductor device including the transistor and a method of manufacturing the semiconductor device. The semiconductor device includes an oxide semiconductor layer including a channel formation region, and a source and drain regi…
Who is the assignee on this patent?
Yokoi Tomokazu, Yamane Yasumasa, Semiconductor Energy Lab
What technology area does this patent fall under?
Primary CPC classification H10P14/3434. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue Feb 03 2015 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).