Light emitting diode

US8946744B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-8946744-B2
Application numberUS-97460510-A
CountryUS
Kind codeB2
Filing dateDec 21, 2010
Priority dateDec 28, 2009
Publication dateFeb 3, 2015
Grant dateFeb 3, 2015

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

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  7. Citations and related patents

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Abstract

Official abstract text for this publication.

The present invention provides a light emitting diode including a lower semiconductor layer formed on a substrate; an upper semiconductor layer disposed above the lower semiconductor layer, exposing an edge region of the lower semiconductor layer; a first electrode formed on the upper semiconductor layer; an insulation layer interposed between the first electrode and the upper semiconductor layer, to supply electric current to the lower semiconductor layer; a second electrode formed on another region of the upper semiconductor layer, to supply electric current to the upper semiconductor layer. The first electrode includes an electrode pad disposed on the upper semiconductor layer and an extension extending from the electrode pad to the exposed lower semiconductor layer. The insulation layer may have a distributed Bragg reflector structure.

First claim

Opening claim text (preview).

What is claimed is: 1. A light emitting diode, comprising: a substrate; a lower semiconductor layer disposed on the substrate; an upper semiconductor layer disposed on the lower semiconductor layer, such that a portion of the lower semiconductor layer is exposed; a first electrode disposed on the upper semiconductor layer and directly on the exposed portion of the lower semiconductor layer, to supply electric current to the lower semiconductor layer; a second electrode for…

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Frequently asked questions

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What does patent US8946744B2 cover?
The present invention provides a light emitting diode including a lower semiconductor layer formed on a substrate; an upper semiconductor layer disposed above the lower semiconductor layer, exposing an edge region of the lower semiconductor layer; a first electrode formed on the upper semiconductor layer; an insulation layer interposed between the first electrode and the upper semiconductor lay…
Who is the assignee on this patent?
Yoon Yeo Jin, Seo Won Cheol, Seoul Viosys Co Ltd
What technology area does this patent fall under?
Primary CPC classification H10H20/841. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue Feb 03 2015 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).