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US-2024414942-A1 · Dec 12, 2024 · US
US8946709B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-8946709-B2 |
| Application number | US-201113045873-A |
| Country | US |
| Kind code | B2 |
| Filing date | Mar 11, 2011 |
| Priority date | Mar 19, 2010 |
| Publication date | Feb 3, 2015 |
| Grant date | Feb 3, 2015 |
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Official abstract text for this publication.
A semiconductor device with a novel structure is provided in which stored data can be held even when power is not supplied and the number of writing is not limited. The semiconductor includes a second transistor and a capacitor over a first transistor. The capacitor includes a source or drain electrode and a gate insulating layer of the second transistor and a capacitor electrode over an insulating layer which covers the second transistor. The gate electrode of the second transistor and the capacitor electrode overlap at least partly with each other with the insulating layer interposed therebetween. By forming the gate electrode of the second transistor and the capacitor electrode using different layers, an integration degree of the semiconductor device can be improved.
Opening claim text (preview).
The invention claimed is: 1. A semiconductor device comprising: a memory cell comprising: a first transistor comprising: a first channel formation region; a first gate insulating layer over the first channel formation region; and a first gate electrode over the first gate insulating layer, the first gate electrode overlapping with the first channel formation region; a second transistor over the first transistor, the second transistor comprising: a second channel formati…
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