Method for manufacturing pillar-shaped semiconductor device
US-9224834-B1 · Dec 29, 2015 · US
Method of making interconnect structure
US8946074B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-8946074-B2 |
| Application number | US-201113285007-A |
| Country | US |
| Kind code | B2 |
| Filing date | Oct 31, 2011 |
| Priority date | Sep 30, 2008 |
| Publication date | Feb 3, 2015 |
| Grant date | Feb 3, 2015 |
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Abstract
Official abstract text for this publication.
A method of forming a semiconductor device, comprising: providing a Si-containing layer; forming a barrier layer over said Si-containing layer, said barrier layer comprising a compound including a metallic element; forming a metallic nucleation_seed layer over said barrier layer, said nucleation_seed layer including said metallic element; and forming a metallic interconnect layer over said nucleation_seed layer, wherein said barrier layer and said nucleation_seed layer are formed without exposing said semiconductor device to the ambient atmosphere.
First claim
Opening claim text (preview).
What is claimed is: 1. A method semiconductor device, comprising: providing a Si-containing layer; forming a metallic contact layer over said Si-containing layer, said contact layer including a metallic element; forming a forming a barrier layer over said Si-containing layer, said barrier layer comprising a compound including said metallic element; forming a metallic nucleation_seed layer over said barrier layer, said nucleation seed layer including said metallic element; an…
Assignees
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Classifications
- H10D64/0111Primary
Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
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- What does patent US8946074B2 cover?
- A method of forming a semiconductor device, comprising: providing a Si-containing layer; forming a barrier layer over said Si-containing layer, said barrier layer comprising a compound including a metallic element; forming a metallic nucleation_seed layer over said barrier layer, said nucleation_seed layer including said metallic element; and forming a metallic interconnect layer over said nucl…
- Who is the assignee on this patent?
- Koerner Heinrich, Infineon Technologies Ag
- What technology area does this patent fall under?
- Primary CPC classification H10D64/0111. Mapped technology areas include Electricity.
- When was this patent published?
- Publication date Tue Feb 03 2015 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
- What related patents are in patentsdb?
- We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).