Methods of forming semiconductor devices
US-2024387699-A1 · Nov 21, 2024 · US
Fabricating method of semiconductor device and semiconductor device fabricated using the same method
US8946069B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-8946069-B2 |
| Application number | US-201314138721-A |
| Country | US |
| Kind code | B2 |
| Filing date | Dec 23, 2013 |
| Priority date | Oct 1, 2010 |
| Publication date | Feb 3, 2015 |
| Grant date | Feb 3, 2015 |
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Abstract
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A fabricating method of a semiconductor device includes providing a substrate having a first region and a second region, forming a plurality of first gates in the first region of the substrate, such that the first gates are spaced apart from each other at a first pitch, forming a plurality of second gates in the second region of the substrate, such that the second gates are spaced apart from each other at a second pitch different from the first pitch, implanting an etch rate adjusting dopant into the second region to form implanted regions, while blocking the first region, forming a first trench by etching the first region between the plurality of first gates, and forming a second trench by etching the second region between the plurality of second gates.
First claim
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What is claimed is: 1. A fabricating method of a semiconductor device, comprising: providing a substrate having a first region and a second region; forming a plurality of first gates in the first region, such that the first gates are spaced apart at a first pitch; forming a plurality of second gates in the second region, such that the second gates are spaced apart at a second pitch different from the first pitch; implanting etch rate adjusting dopants in regions between the…
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Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
- H10P30/204Primary
Electricity · mapped topic
Electricity · mapped topic
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- What does patent US8946069B2 cover?
- A fabricating method of a semiconductor device includes providing a substrate having a first region and a second region, forming a plurality of first gates in the first region of the substrate, such that the first gates are spaced apart from each other at a first pitch, forming a plurality of second gates in the second region of the substrate, such that the second gates are spaced apart from ea…
- Who is the assignee on this patent?
- Samsung Electronics Co Ltd, Samsung Electronics Co Ltd
- What technology area does this patent fall under?
- Primary CPC classification H10P30/204. Mapped technology areas include Electricity.
- When was this patent published?
- Publication date Tue Feb 03 2015 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
- What related patents are in patentsdb?
- We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).