Method for fabricating capacitor

Patent metadata

Field	Value
Publication number	US-8946047-B2
Application number	US-79441210-A
Country	US
Kind code	B2
Filing date	Jun 4, 2010
Priority date	Nov 3, 2005
Publication date	Feb 3, 2015
Grant date	Feb 3, 2015

Abstract

A method for fabricating a capacitor includes: forming a storage node contact plug over a substrate; forming an insulation layer having an opening exposing a surface of the storage node contact plug over the storage contact plug; forming a conductive layer for a storage node over the insulation layer and the exposed surface of the storage node contact plug through two steps performed at different temperatures; performing an isolation process to isolate parts of the conductive layer; and sequentially forming a dielectric layer and a plate electrode over the isolated conductive layer.

First claim

What is claimed is:

1. A method for fabricating a capacitor, comprising:
forming a storage node contact plug over a substrate;
forming an etch stop layer over the storage node contact plug;
forming an insulation layer over the etch stop layer;
forming a first opening exposing a surface of the etch stop layer by etching a portion of the insulation layer;
forming a second opening exposing only an entire surface of the storage node contact plug by etching a portion of the etch stop layer;
forming a catalytic layer over the entire surface of the insulation layer including the first opening and the etch stop layer including the second opening;
forming a conductive layer for a storage node over the entire surface of the catalytic layer;
performing an isolation process to isolate parts of the conductive layer;
removing the catalytic layer and the insulation layer formed over the etch stop layer, thereby allowing a remaining catalytic layer to cover a sidewall of the etch stop layer, the entire surface of a storage node contact plug, and a bottom portion of a conductive layer in the second opening; and
sequentially forming a dielectric layer and a plate electrode over the isolated parts of the conductive layer,
wherein forming the conductive layer for the storage node over the entire surface of the catalytic layer includes forming a layer of a material selected from the group consisting of ruthenium (Ru), platinum (Pt), iridium (Ir), rhodium (Rh), palladium (Pd), hafnium (Hf), a nitrided film thereof, and a conductive oxide layer.

2. The method of claim 1 , wherein forming the catalytic layer includes forming a layer of a material selected from the group consisting of palladium (Pd), a tungsten nitride (WN) layer, and tungsten nitride carbon (WNC).

3. The method of claim 2 , wherein the catalytic layer is formed using a method selected from the group consisting of an atomic layer deposition (ALD) method, a plasma enhanced atomic layer deposition (PEALD) method, a chemical vapor deposition (CVD) method, and a plasma enhanced chemical vapor deposition (PECVD) method.

4. The method of claim 1 , wherein forming the catalytic layer comprises forming the catalytic layer in a thickness ranging from approximately 10 Å to approximately 50 Å.

5. The method of claim 1 , wherein the conductive layer is formed using one of an atomic layer deposition (ALD) method and a combination of an ALD method and a chemical vapor deposition (CVD) method.

6. The method of claim 5 , further comprising performing a plasma treatment when a reaction gas is flowed during one of the ALD method and the combination of the ALD method and the CVD method.

7. The method of claim 6 , wherein the plasma treatment is performed using a gas selected from a group consisting of oxygen (O 2 ), ammonia (NH 3 ), dyhydrogen oxide (H 2 O), hydrazine (N 2 H 4 ), Me 2 N 2 H 2 , hydrogen (H 2 ), and a combination thereof at a plasma power ranging from approximately 10 W to approximately 2,000 W, and a temperature ranging from approximately 200° C. to approximately 500° C.

8. The method of claim 1 , wherein forming the conductive layer comprises forming the storage node in a thickness ranging from approximately 100 Å to approximately 200 Å.

9. The method of claim 1 , wherein the insulation layer and the catalytic layer formed over the etch stop layer are removed through a dip-out process.

10. The method of claim 1 , wherein after the removing of the exposed part of the catalytic layer, the catalytic layer is remained beneath the isolated parts of the conductive layer.

Assignees

• Kim Jin-Hyock
• Yeom Seung-Jin
• Park Ki-Seon
• Song Han-Sang
• Kil Deok-Sin
• Roh Jae-Sung
• Sk Hynix Inc

Inventors

• Kim Jin-Hyock
• Yeom Seung-Jin
• Park Ki-Seon
• Song Han-Sang
• Kil Deok-Sin
• Roh Jae-Sung

Classifications

• H10D1/716

  having vertical extensions · CPC title

• H10D1/694

  comprising noble metals or noble metal oxides · CPC title

• H10D1/692

  Electrodes · CPC title

• H10D1/682 Primary

  having dielectrics comprising perovskite structures · CPC title

• H10D1/042

  using deposition processes to form electrode extensions · CPC title