Replacement gates to enhance transistor strain

Patent metadata

Field	Value
Publication number	US-8946016-B2
Application number	US-201313909792-A
Country	US
Kind code	B2
Filing date	Jun 4, 2013
Priority date	Dec 16, 2005
Publication date	Feb 3, 2015
Grant date	Feb 3, 2015

Abstract

Some embodiments of the present invention include apparatuses and methods relating to NMOS and PMOS transistor strain.

First claim

What is claimed is:

1. A method comprising:
forming a substrate;
forming a PMOS transistor on the substrate, wherein the PMOS transistor comprises a first gate structure disposed on a first channel and first stressor, wherein the first stressor comprises an epitaxial source and drain film, and first sidewall spacers disposed adjacent the first gate structure;
forming an NMOS transistor on the substrate, wherein the NMOS transistor comprises a second gate structure disposed on…

Assignees

• Intel Corp

Inventors

• Bohr Mark T

Classifications

• H10D64/01318 Primary

  Electricity · mapped topic

• H10D64/013

  Electricity · mapped topic

• H10D84/0167

  Electricity · mapped topic

• H10D62/822

  Electricity · mapped topic

• H10D84/907

  Electricity · mapped topic