Metal gates for semiconductor devices and method thereof
US-2024429281-A1 · Dec 26, 2024 · US
US8946006B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-8946006-B2 |
| Application number | US-91392210-A |
| Country | US |
| Kind code | B2 |
| Filing date | Oct 28, 2010 |
| Priority date | Oct 28, 2010 |
| Publication date | Feb 3, 2015 |
| Grant date | Feb 3, 2015 |
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A disposable dielectric spacer is formed on sidewalls of a disposable material stack. Raised source/drain regions are formed on planar source/drain regions by selective epitaxy. The disposable dielectric spacer is removed to expose portions of a semiconductor layer between the disposable material stack and the source/drain regions including the raised source/drain regions. Dopant ions are implanted to form source/drain extension regions in the exposed portions of the semiconductor layer. A gate-level dielectric layer is deposited and planarized. The disposable material stack is removed and a gate stack including a gate dielectric and a gate electrode fill a cavity formed by removal of the disposable material stack. Optionally, an inner dielectric spacer may be formed on sidewalls of the gate-level dielectric layer within the cavity prior to formation of the gate stack to tailor a gate length of a field effect transistor.
Opening claim text (preview).
What is claimed is: 1. A method of forming a semiconductor structure comprising: forming a disposable material stack on a semiconductor substrate; forming a single unitary disposable dielectric spacer on sidewalls of said disposable material stack, wherein a base of the single unitary disposable dielectric spacer is in direct contact with the semiconductor substrate, and wherein said single unitary disposable dielectric spacer is composed of a single material; forming planar s…
Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
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