Replacement gate MOSFET with raised source and drain

US8946006B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-8946006-B2
Application numberUS-91392210-A
CountryUS
Kind codeB2
Filing dateOct 28, 2010
Priority dateOct 28, 2010
Publication dateFeb 3, 2015
Grant dateFeb 3, 2015

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Abstract

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A disposable dielectric spacer is formed on sidewalls of a disposable material stack. Raised source/drain regions are formed on planar source/drain regions by selective epitaxy. The disposable dielectric spacer is removed to expose portions of a semiconductor layer between the disposable material stack and the source/drain regions including the raised source/drain regions. Dopant ions are implanted to form source/drain extension regions in the exposed portions of the semiconductor layer. A gate-level dielectric layer is deposited and planarized. The disposable material stack is removed and a gate stack including a gate dielectric and a gate electrode fill a cavity formed by removal of the disposable material stack. Optionally, an inner dielectric spacer may be formed on sidewalls of the gate-level dielectric layer within the cavity prior to formation of the gate stack to tailor a gate length of a field effect transistor.

First claim

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What is claimed is: 1. A method of forming a semiconductor structure comprising: forming a disposable material stack on a semiconductor substrate; forming a single unitary disposable dielectric spacer on sidewalls of said disposable material stack, wherein a base of the single unitary disposable dielectric spacer is in direct contact with the semiconductor substrate, and wherein said single unitary disposable dielectric spacer is composed of a single material; forming planar s…

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What does patent US8946006B2 cover?
A disposable dielectric spacer is formed on sidewalls of a disposable material stack. Raised source/drain regions are formed on planar source/drain regions by selective epitaxy. The disposable dielectric spacer is removed to expose portions of a semiconductor layer between the disposable material stack and the source/drain regions including the raised source/drain regions. Dopant ions are impla…
Who is the assignee on this patent?
Ponoth Shom, Horak David V, Yang Chih-Chao, and 1 more
What technology area does this patent fall under?
Primary CPC classification H10D64/017. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue Feb 03 2015 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).