Internal electrical contact for enclosed MEMS devices

US8945969B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-8945969-B2
Application numberUS-201414456973-A
CountryUS
Kind codeB2
Filing dateAug 11, 2014
Priority dateJan 30, 2013
Publication dateFeb 3, 2015
Grant dateFeb 3, 2015

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Abstract

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A method of fabricating electrical connections in an integrated MEMS device is disclosed. The method comprises forming a MEMS wafer. Forming a MEMS wafer includes forming one cavity in a first semiconductor layer, bonding the first semiconductor layer to a second semiconductor layer with a dielectric layer disposed between the first semiconductor layer and the second semiconductor layer, and etching at least one via through the second semiconductor layer and the dielectric layer and depositing a conductive material on the second semiconductor layer and filling the at least one via. Forming a MEMS wafer also includes patterning and etching the conductive material to form one standoff and depositing a germanium layer on the conductive material, patterning and etching the germanium layer, and patterning and etching the second semiconductor layer to define one MEMS structure. The method also includes bonding the MEMS wafer to a base substrate.

First claim

Opening claim text (preview).

What is claimed is: 1. A method of fabricating electrical connections in an integrated MEMS device comprising: forming a MEMS substrate comprising: depositing a dielectric layer on a handle layer; patterning and etching the dielectric layer to form at least one via to the handle layer; depositing a silicon layer on the dielectric layer and into the at least one via; patterning and etching the silicon layer to define one or more MEMS structures; etching the dielectric laye…

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What does patent US8945969B2 cover?
A method of fabricating electrical connections in an integrated MEMS device is disclosed. The method comprises forming a MEMS wafer. Forming a MEMS wafer includes forming one cavity in a first semiconductor layer, bonding the first semiconductor layer to a second semiconductor layer with a dielectric layer disposed between the first semiconductor layer and the second semiconductor layer, and et…
Who is the assignee on this patent?
Invensense Inc
What technology area does this patent fall under?
Primary CPC classification B81C1/00301. Mapped technology areas include Operations & Transport.
When was this patent published?
Publication date Tue Feb 03 2015 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).