Method for fabricating variable resistance memory device

Patent metadata

Field	Value
Publication number	US-8945949-B2
Application number	US-201213595567-A
Country	US
Kind code	B2
Filing date	Aug 27, 2012
Priority date	Dec 28, 2011
Publication date	Feb 3, 2015
Grant date	Feb 3, 2015

Abstract

A method for fabricating a variable resistance memory device in accordance with an embodiment of the present invention includes: sequentially forming a first conductive layer and a variable resistance layer on a substrate; forming stacked structures in which first conductive lines and variable resistance lines are sequentially stacked by selectively etching the variable resistance layer and the first conductive layer; forming an insulating layer to fill a space between the stacked structures; forming a second conductive layer on the insulating layer and the stacked structures; and forming a second conductive line and a variable resistance pattern by etching the second conductive layer and the variable resistance line using mask patterns in a line type extending in a direction intersecting the stacked structures.

First claim

What is claimed is:

1. A method for fabricating a variable resistance memory device, comprising:
sequentially forming a first conductive layer and a variable resistance layer on a substrate;
forming stacked structures in which first conductive lines and variable resistance lines are sequentially stacked by selectively etching the variable resistance layer and the first conductive layer;
forming an insulating layer to fill a space between the stacked structures;
forming a sec…

Assignees

• Hwang Sang Min
• Sk Hynix Inc

Inventors

• Hwang Sang Min

Classifications

• H10N50/01 Primary

  Electricity · mapped topic

• H10N70/20

  Electricity · mapped topic

• H10N70/063

  Electricity · mapped topic

• H10N70/021

  Electricity · mapped topic

• H10B61/00

  Electricity · mapped topic