Resist composition and pattern forming process
US-2024377730-A1 · Nov 14, 2024 · US
Electronic device, and method for manufacturing symbol on exterior of electronic device
US8945406B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-8945406-B2 |
| Application number | US-201213604698-A |
| Country | US |
| Kind code | B2 |
| Filing date | Sep 6, 2012 |
| Priority date | Sep 6, 2011 |
| Publication date | Feb 3, 2015 |
| Grant date | Feb 3, 2015 |
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Abstract
Official abstract text for this publication.
A method for manufacturing a symbol on an exterior of an electronic device is provided. The method includes preparing a support layer, preparing a nanograting layer on the support layer, the nanograting layer including a first nanograting area corresponding to a preset symbol and a second nanograting area corresponding to an area other than the preset symbol, wherein each of the first nanograting area and the second nanograting area includes three-dimensional (3D) nanostructures and a pitch between the 3D nanostructures arranged in the first nanograting area is different from a pitch between the 3D nanostructures arranged in the second nanograting area.
First claim
Opening claim text (preview).
What is claimed is: 1. A method for manufacturing a symbol on an exterior of an electronic device, the method comprising: preparing a support layer; and preparing a nanograting layer on the support layer, the nanograting layer including a first nanograting area corresponding to a preset symbol and a second nanograting area corresponding to an area other than the preset symbol, wherein the first nanograting area includes three-dimensional (3D) nanostructures arranged a first pi…
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Cross-Sectional Technologies · mapped topic
- G03F7/20Primary
Physics · mapped topic
Cross-Sectional Technologies · mapped topic
Physics · mapped topic
Physics · mapped topic
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Frequently asked questions
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- What does patent US8945406B2 cover?
- A method for manufacturing a symbol on an exterior of an electronic device is provided. The method includes preparing a support layer, preparing a nanograting layer on the support layer, the nanograting layer including a first nanograting area corresponding to a preset symbol and a second nanograting area corresponding to an area other than the preset symbol, wherein each of the first nanograti…
- Who is the assignee on this patent?
- Chung Seong-Eun, Jung Il-Yong, Samsung Electronics Co Ltd
- What technology area does this patent fall under?
- Primary CPC classification G03F7/20. Mapped technology areas include Physics.
- When was this patent published?
- Publication date Tue Feb 03 2015 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
- What related patents are in patentsdb?
- We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).