Selective cuts to remove predicted interconnect bulging regions
US-2024419882-A1 · Dec 19, 2024 · US
US8943451B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-8943451-B2 |
| Application number | US-201113167415-A |
| Country | US |
| Kind code | B2 |
| Filing date | Jun 23, 2011 |
| Priority date | Jun 23, 2010 |
| Publication date | Jan 27, 2015 |
| Grant date | Jan 27, 2015 |
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The invention provides techniques and apparatuses for generating a hierarchical representation of the power behavior of an electronic design. In some implementations, a flat finite state machine, representing the power behavior of an electronic design is extracted from the power specification for the electronic design. Subsequently, a hierarchical finite state machine representation for the power behavior is generated from the flat finite state machine, the power specification and the logical specification.
Opening claim text (preview).
What is claimed is: 1. A method comprising: generating, by a computing system, a flat finite state machine representation of at least a portion of an electronic design based, at least in part, on power state information described in a power specification of the electronic design; identifying, by the computing system, relationships between power states, between transitions associated with the power states, or between at least one of the power states and at least one of the transi…
Physics · mapped topic
Physics · mapped topic
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