Controlling nonvolatile memory device and nonvolatile memory system
US-9195541-B2 · Nov 24, 2015 · US
Signal transmission/reception circuit
US8943389B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-8943389-B2 |
| Application number | US-201213599490-A |
| Country | US |
| Kind code | B2 |
| Filing date | Aug 30, 2012 |
| Priority date | Sep 14, 2011 |
| Publication date | Jan 27, 2015 |
| Grant date | Jan 27, 2015 |
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Abstract
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A data buffer section stores input words, and outputs them to a first signal line group in order. An error checking and correcting code is generated that has the same number of bits as the words. Some bits are not to be output at the same time within the range of the first and second signal line groups or within the range of a partial signal line group included in the first and second signal line groups. A code transmission section outputs the error checking and correcting code to different signal lines of the second signal line group respectively, such that a plurality of bits in a code word are not output at the same time within the range of the first and second signal line groups or within the range of a partial signal line group included in the first and second signal line groups.
First claim
Opening claim text (preview).
The invention claimed is: 1. A signal transmission/reception circuit comprising a signal transmission circuit and a signal reception circuit connected with each other by a first signal line group and a second signal line group, wherein the signal transmission circuit comprises: a transmission-side data buffer section comprising k transmission-side shift registers each having k stages where the number of bits of a word is k, that inputs respective bits of an input word to the k tr…
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Classifications
Electricity · mapped topic
- H03M13/05Primary
Electricity · mapped topic
Electricity · mapped topic
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- What does patent US8943389B2 cover?
- A data buffer section stores input words, and outputs them to a first signal line group in order. An error checking and correcting code is generated that has the same number of bits as the words. Some bits are not to be output at the same time within the range of the first and second signal line groups or within the range of a partial signal line group included in the first and second signal li…
- Who is the assignee on this patent?
- Takahashi Tsugio, Nec Corp
- What technology area does this patent fall under?
- Primary CPC classification H03M13/05. Mapped technology areas include Electricity.
- When was this patent published?
- Publication date Tue Jan 27 2015 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
- What related patents are in patentsdb?
- We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).