User-space emulation framework for heterogeneous soc design
US-2024004776-A1 · Jan 4, 2024 · US
US8943369B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-8943369-B2 |
| Application number | US-201213396001-A |
| Country | US |
| Kind code | B2 |
| Filing date | Feb 14, 2012 |
| Priority date | Feb 21, 2011 |
| Publication date | Jan 27, 2015 |
| Grant date | Jan 27, 2015 |
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An electronic tracing process includes packing both stall ( 215 ) and reason ( 219 ) data into a single high priority timing information stream. An integrated circuit includes an electronic processor ( 110 ), and a tracing circuit ( 120 ) operable to pack both stall and events data into a single timing information stream. Other circuits, processes and systems are also disclosed.
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What is claimed is: 1. An electronic tracing process comprising: packing both stall and reason data into a single high priority timing information stream, and selectively prioritizing the stall and reason data into the single high priority timing information stream over PC trace and data trace, wherein the PC trace includes program flow activity and the data trace includes a trace of instruction bus data and data bus data for tracing load/store data accesses.…
Physics · mapped topic
Physics · mapped topic
Physics · mapped topic
Physics · mapped topic
Physics · mapped topic
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