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US-11868774-B2 · Jan 9, 2024 · US
Storing branch information in an address table of a processor
US8943301B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-8943301-B2 |
| Application number | US-201113101650-A |
| Country | US |
| Kind code | B2 |
| Filing date | May 5, 2011 |
| Priority date | Feb 2, 2005 |
| Publication date | Jan 27, 2015 |
| Grant date | Jan 27, 2015 |
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Abstract
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Methods for storing branch information in an address table of a processor are disclosed. A processor of the disclosed embodiments may generally include an instruction fetch unit connected to an instruction cache, a branch execution unit, and an address table being connected to the instruction fetch unit and the branch execution unit. The address table may generally be adapted to store a plurality of entries with each entry of the address table being adapted to store a base address and a base instruction tag. In a further embodiment, the branch execution unit may be adapted to determine the address of a branch instruction having an instruction tag based on the base address and the base instruction tag of an entry of the address table associated with the instruction tag. In some embodiments, the address table may further be adapted to store branch information.
First claim
Opening claim text (preview).
What is claimed is: 1. A method, in a processor of a data processing system, for performing branch operations, comprising: fetching, by an instruction fetch unit of the processor, an instruction to be executed; retrieving, from a single address table structure of the processor, instruction information for the fetched instruction; and performing, by a branch execution unit of the processor, a branch operation based on the received instruction and the instruction information ret…
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- G06F9/3806Primary
Physics · mapped topic
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Frequently asked questions
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- What does patent US8943301B2 cover?
- Methods for storing branch information in an address table of a processor are disclosed. A processor of the disclosed embodiments may generally include an instruction fetch unit connected to an instruction cache, a branch execution unit, and an address table being connected to the instruction fetch unit and the branch execution unit. The address table may generally be adapted to store a plurali…
- Who is the assignee on this patent?
- Konigsburg Brian R, Levitan David Stephen, Sauer Wolfram M, and 2 more
- What technology area does this patent fall under?
- Primary CPC classification G06F9/3806. Mapped technology areas include Physics.
- When was this patent published?
- Publication date Tue Jan 27 2015 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
- What related patents are in patentsdb?
- We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).