Address Range Based Memory Hints for Prefetcher, Cache and Memory Controller
US-2024385966-A1 · Nov 21, 2024 · US
Virtual address mapping using rule based aliasing to achieve fine grained page translation
US8943296B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-8943296-B2 |
| Application number | US-201113096755-A |
| Country | US |
| Kind code | B2 |
| Filing date | Apr 28, 2011 |
| Priority date | Apr 28, 2011 |
| Publication date | Jan 27, 2015 |
| Grant date | Jan 27, 2015 |
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Abstract
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One or more unused bits of a virtual address range are allocated for aliasing so that multiple virtually addressed sub-pages can be mapped to a common memory page. When one bit is allocated for aliasing, dirty bit information can be provided at a granularity that is one-half of a memory page. When M bits are allocated for aliasing, dirty bit information can be provided at a granularity that is 1/(2 M )-th of a memory page.
First claim
Opening claim text (preview).
What is claimed is: 1. A method of translating virtual addresses to physical memory pages in a computer system, comprising: receiving a first binary representation of a virtual address to be translated; modifying the first binary representation to generate a second binary representation by copying M bit values from bit position N through bit position N−(M−1) of the first binary representation to bit position L through bit position L−(M−1) of the first binary representation, wher…
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- G06F12/1027Primary
Physics · mapped topic
Physics · mapped topic
Physics · mapped topic
- G06F11/1451Primary
Physics · mapped topic
Physics · mapped topic
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Frequently asked questions
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- What does patent US8943296B2 cover?
- One or more unused bits of a virtual address range are allocated for aliasing so that multiple virtually addressed sub-pages can be mapped to a common memory page. When one bit is allocated for aliasing, dirty bit information can be provided at a granularity that is one-half of a memory page. When M bits are allocated for aliasing, dirty bit information can be provided at a granularity that is …
- Who is the assignee on this patent?
- Serebrin Benjamin C, Mehta Bhavesh, Vmware Inc
- What technology area does this patent fall under?
- Primary CPC classification G06F12/1027. Mapped technology areas include Physics.
- When was this patent published?
- Publication date Tue Jan 27 2015 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
- What related patents are in patentsdb?
- We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).