Victim cache that supports draining write-miss entries
US-2024264952-A1 · Aug 8, 2024 · US
Configurable cache and method to configure same
US8943293B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-8943293-B2 |
| Application number | US-201414219034-A |
| Country | US |
| Kind code | B2 |
| Filing date | Mar 19, 2014 |
| Priority date | Mar 3, 2009 |
| Publication date | Jan 27, 2015 |
| Grant date | Jan 27, 2015 |
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Abstract
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A method includes receiving an address at a tag state array of a cache, wherein the cache is configurable to have a first size and a second size that is smaller than the first size. The method further includes identifying a first portion of the address as a set index, wherein the first portion has a same number of bits when the cache has the first size as when the cache has the second size. The method further includes using the set index to locate at least one tag field of the tag state array, identifying a second portion of the address to compare to a value stored at the at least one tag field, locating at least one state field of the tag state array that is associated with a particular tag field that matches the second portion, identifying a cache line based on a comparison of a third portion of the address to at least one status bit of the at least one state field when the cache has the second size, and retrieving the cache line.
First claim
Opening claim text (preview).
What is claimed is: 1. A method comprising: receiving an address at a tag state array of a cache, wherein the cache is configurable to have at least two different sizes; identifying a first portion of the address as a set index; locating at least one state field of the tag state array; identifying a cache line of the cache based on a comparison of a second portion of the address to status bits of the at least one state field, wherein a number of bits of the second portion of…
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Classifications
- G06F12/0895Primary
Physics · mapped topic
Physics · mapped topic
Physics · mapped topic
- G06F12/0802Primary
Physics · mapped topic
Physics · mapped topic
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- What does patent US8943293B2 cover?
- A method includes receiving an address at a tag state array of a cache, wherein the cache is configurable to have a first size and a second size that is smaller than the first size. The method further includes identifying a first portion of the address as a set index, wherein the first portion has a same number of bits when the cache has the first size as when the cache has the second size. The…
- Who is the assignee on this patent?
- Qualcomm Inc
- What technology area does this patent fall under?
- Primary CPC classification G06F12/0895. Mapped technology areas include Physics.
- When was this patent published?
- Publication date Tue Jan 27 2015 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
- What related patents are in patentsdb?
- We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).