Determining transistor leakage for an integrated circuit

Patent metadata

Field	Value
Publication number	US-8942932-B2
Application number	US-87291610-A
Country	US
Kind code	B2
Filing date	Aug 31, 2010
Priority date	Aug 31, 2010
Publication date	Jan 27, 2015
Grant date	Jan 27, 2015

Abstract

Techniques are disclosed relating to determining power consumption of an integrated circuit. In one embodiment, an integrated circuit is disclosed that includes a power monitor unit configured to receive a temperature of the integrated circuit, and to determine an estimate of power consumed by transistor leakage of the integrated circuit based on the received temperature. In one embodiment, to determine the estimate, the power monitor unit is configured to multiply a base value and a scaling factor that is adjusted based on the received temperature. In some embodiments, the power monitor unit is configured to receive performance state information of the integrated circuit, and to determine an estimate of power consumed by transistor leakage of the integrated circuit based on the performance state information.

First claim

What is claimed is:

1. An integrated circuit, comprising:
a power monitor unit configured to:
receive a temperature of the integrated circuit and performance state information specifying a performance state of the integrated circuit, wherein the performance state is a state in which the integrated circuit is configured to execute instructions at a particular voltage and a particular frequency, and wherein the performance state is a performance state in accordance with an Advanced Configuration and Power Interface (ACPI) standard; and
determine an estimate of power consumed by transistor leakage of the integrated circuit based on the received temperature and the performance state information.

2. The integrated circuit of claim 1 , wherein, to determine the estimate, the power monitor unit is configured to:
adjust a scaling factor based on the received temperature; and
multiply a base value and the adjusted scaling factor to produce the estimate.

3. The integrated circuit of claim 2 , wherein the power monitor unit is configured to select the scaling factor from a plurality of scaling factors based on the performance state of the integrated circuit.

4. The integrated circuit of claim 3 , further comprising:
a memory storing the base value and the plurality of scaling factors, wherein the memory is implemented using blown fuses.

5. The integrated circuit of claim 2 , wherein the base value corresponds to an estimate of power consumed by the integrated circuit during one or more maximum operating conditions.

6. The integrated circuit of claim 1 , wherein the integrated circuit is configured to:
determine a total power estimate of power consumed by the integrated circuit based on the estimate of power consumed by transistor leakage; and
implement a performance state based on the total power estimate.

7. The integrated circuit of claim 6 , wherein the total power estimate is further determined based on an estimate of power consumed by transistor switching of the integrated circuit.

8. The integrated circuit of claim 1 , further comprising:
a temperature sensor configured to determine the temperature of the integrated circuit.

9. The integrated circuit of claim 1 , wherein the integrated circuit is configured to:
determine the temperature based on one or more power measurements without using a temperature sensor.

10. A processor, comprising:
a power monitor unit configured to:
receive performance state information of the processor, wherein the performance state information specifies an Advanced Configuration and Power Interface (ACPI) performance state, wherein the ACPI performance state is indicative of a state in which the processor operates at a particular one of a plurality of voltages and a particular one of a plurality of frequencies; and
determine an estimate of power consumed by transistor leakage of the processor based on the performance state information.

11. The processor of claim 10 , wherein, to determine the estimate, the power monitor unit is configured to multiply a base estimate and a scaling factor, wherein the power monitor unit is configured to select the scaling factor from among a plurality of scaling factors based on the received performance state information.

12. The processor of claim 11 , wherein the power monitor unit is configured to:
receive a temperature of the processor; and
adjust the scaling factor based on the temperature prior to multiplying the base estimate and the scaling factor.

13. The processor of claim 10 , wherein the power monitor unit is further configured to determine an estimate of power consumed by transistor switching of the processor; and
wherein the processor is configured to implement a performance state based on the estimate of power consumed by transistor leakage and the estimate of power consumed by transistor switching.

14. The processor of claim 10 , further comprising:
a plurality of cores;
wherein the received performance state information includes a performance state of a first core of the plurality of cores, and wherein the determined estimate is an estimate of power consumed by transistor leakage of the first core of the processor.

15. A method, comprising:
a processor obtaining a base estimate of power consumed by transistor leakage of the processor; and
the processor scaling the base estimate based on a performance state of the processor and a temperature of the processor, wherein the performance state is a performance state in accordance with an Advanced Configuration and Power Interface (ACPI) standard.

16. The method of claim 15 , further comprising:
the processor determining an estimate of power consumed by transistor switching of the processor; and
the processor adding the scaled base estimate and the estimate of power consumed by transistor switching to calculate a total amount of power consumed by the processor.

17. The method of claim 16 , further comprising:
the processor implementing a performance state based on the total amount of power consumed by the processor.

18. The method of claim 15 , wherein the base value corresponds to an estimate of the power consumed by the processor during one or more maximum operating conditions.

19. The method of claim 15 , wherein the temperature is an average temperature calculated based on a plurality of temperatures of the processor.

20. A non-transitory computer readable medium comprising a data structure which is operated upon by a program executable on a computer system, the program operating on the data structure to perform a portion of a process to fabricate an integrated circuit including circuitry described by the data structure, the circuitry described in the data structure including:
a power monitor unit configured to receive a temperature of the integrated circuit and an indication of a performance state at which the integrated circuit operates, wherein the performance state is a performance state in accordance with an Advanced Configuration and Power Interface (ACPI) standard;
wherein the power monitor unit is configured to determine an estimate of power consumed by transistor leakage of the integrated circuit, wherein the estimate is based on the received temperature and the performance state.

21. The computer readable medium of claim 20 , wherein the storage medium stores hardware description language (HDL) data, Verilog data, or graphic database system II (GDSII) data.

Assignees

• Naffziger Samuel D
• Advanced Micro Devices Inc

Inventors

• Naffziger Samuel D

Classifications

• G06F1/3206 Primary

  Monitoring of events, devices or parameters that trigger a change in power modality · CPC title