Image processing apparatus and method

US8942494B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-8942494-B2
Application numberUS-201213671000-A
CountryUS
Kind codeB2
Filing dateNov 7, 2012
Priority dateNov 15, 2011
Publication dateJan 27, 2015
Grant dateJan 27, 2015

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  5. First independent claim

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Abstract

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An image processing apparatus including a decoding unit configured to decode encoded stereoscopic dynamic image data containing a consecutive picture pair having a disparity, for each block into which the picture has been divided, and to detect a decoding error, an estimation unit configured to perform first estimation processing of estimating, as a disparity of an error block between an error picture including an error block in which the decoding error has been detected and a paired picture thereof, a disparity of a corresponding-location corresponding to the error block between an approximate picture and a paired picture thereof, and a correction unit configured to correct the decoding error by applying, to the error block, a block located at a position shifted by an amount of the estimated disparity from the corresponding-location in the paired picture of the error picture.

First claim

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What is claimed is: 1. An image processing apparatus, comprising: a decoding unit configured to decode encoded stereoscopic dynamic image data containing a plurality of picture pairs each having a disparity, for each block into which the picture is divided, and to detect an error block in which a decoding error is generated while decoding; an estimation unit configured to perform a first estimation processing including detecting, among pictures which are decoded prior to an err…

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What does patent US8942494B2 cover?
An image processing apparatus including a decoding unit configured to decode encoded stereoscopic dynamic image data containing a consecutive picture pair having a disparity, for each block into which the picture has been divided, and to detect a decoding error, an estimation unit configured to perform first estimation processing of estimating, as a disparity of an error block between an error …
Who is the assignee on this patent?
Fujitsu Semiconductor Ltd
What technology area does this patent fall under?
Primary CPC classification H04N19/573. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue Jan 27 2015 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).