Resistor-based Σ-ΔDAC

US8941520B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-8941520-B2
Application numberUS-201113995156-A
CountryUS
Kind codeB2
Filing dateSep 30, 2011
Priority dateSep 30, 2011
Publication dateJan 27, 2015
Grant dateJan 27, 2015

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Abstract

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An inverter-driven resistor-ladder digital-to-analog (DAC) converter includes a resistor-ladder network that comprises a resistor for each bit signal of a multi-bit input signal. Each resistor of the resistor-ladder network comprises an input end and an output end. The input end of each resistor is coupled to a corresponding bit signal of the multi-bit input signal, and the output end of each resistor is coupled to an output node of the resistor-ladder network. An output voltage is generated at the output node that is based on the multi-bit input signal. In one exemplary embodiment, the multi-bit input signal is a sigma-delta (ΣΔ) modulated multi-bit input signal. In another exemplary embodiment, resistance values of the resistors of the resistor-ladder network are related by a binary weighting. In still another exemplary embodiment, resistance values of the resistors of the resistor-ladder network are substantially equal.

First claim

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What is claimed is: 1. A digital-to-analog converter, comprising an inverter-driven resistor-ladder network comprising a resistor for each bit signal of a multi-bit input signal, the multi-bit input signal comprising a plurality of bits, each resistor of the resistor-ladder network comprising an input end and an output end, the input end of each resistor being coupled to a corresponding bit signal of the multi-bit input signal, and the output end of each resistor being coupled to a…

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What does patent US8941520B2 cover?
An inverter-driven resistor-ladder digital-to-analog (DAC) converter includes a resistor-ladder network that comprises a resistor for each bit signal of a multi-bit input signal. Each resistor of the resistor-ladder network comprises an input end and an output end. The input end of each resistor is coupled to a corresponding bit signal of the multi-bit input signal, and the output end of each r…
Who is the assignee on this patent?
Kim Hyung Seok, Li Yee W, Ravi Ashoke, and 2 more
What technology area does this patent fall under?
Primary CPC classification H03M1/0863. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue Jan 27 2015 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).