Package substrate and semiconductor package including the same
US-2024429153-A1 · Dec 26, 2024 · US
Using collapse limiter structures between elements to reduce solder bump bridging
US8941236B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-8941236-B2 |
| Application number | US-201213631713-A |
| Country | US |
| Kind code | B2 |
| Filing date | Sep 28, 2012 |
| Priority date | Sep 28, 2012 |
| Publication date | Jan 27, 2015 |
| Grant date | Jan 27, 2015 |
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Abstract
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Provided are an electronic assembly and method for forming the same, comprising a first element having a first surface and a second element having a second surface. Electrical connections are provided between the first and the second elements formed by heating solder bumps. At least one collapse limiter structure is coupled to at least one of the first and the second surfaces, wherein the at least one collapse limiter structure is between at least two of the electrical connections.
First claim
Opening claim text (preview).
What is claimed: 1. An electronic assembly, comprising: a first element having a first surface; a second element having a second surface; electrical connections between the first and the second elements formed by heating solder bumps; and a plurality of collapse limiter structures coupled to at least one of the first and the second surfaces, wherein the plurality of collapse limiter structures are dispersed in an array of the electrical connections, wherein the array include…
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Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
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- What does patent US8941236B2 cover?
- Provided are an electronic assembly and method for forming the same, comprising a first element having a first surface and a second element having a second surface. Electrical connections are provided between the first and the second elements formed by heating solder bumps. At least one collapse limiter structure is coupled to at least one of the first and the second surfaces, wherein the…
- Who is the assignee on this patent?
- Limaye Ameya, Harries Richard J, Sane Sandeep B, and 1 more
- What technology area does this patent fall under?
- Primary CPC classification H10W90/701. Mapped technology areas include Electricity.
- When was this patent published?
- Publication date Tue Jan 27 2015 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
- What related patents are in patentsdb?
- We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).