Sealed semiconductor device having adhesive patch with inwardly sloped side surfaces

Patent metadata

Field	Value
Publication number	US-8941226-B2
Application number	US-201313965521-A
Country	US
Kind code	B2
Filing date	Aug 13, 2013
Priority date	Aug 8, 2011
Publication date	Jan 27, 2015
Grant date	Jan 27, 2015

Abstract

A semiconductor device has an external terminal formed through the use of an electrolysis plating method. A front surface of a semiconductor wafer is placed over a front surface of a first support heated to a first temperature. An adhesive sheet is then bonded to a back surface of the semiconductor wafer, after which the semiconductor wafer is subjected to heat treatment at a second temperature higher than the first temperature. After the semiconductor wafer and the adhesive sheet are cut along cutting regions, a plurality of semiconductor chips each having an adhesive patch bonded thereto are obtained. A mother substrate is placed over a front surface of a second support heated to a third temperature and the semiconductor chips are fixed to an upper surface of the mother substrate via the adhesive patch.

First claim

What is claimed is:

1. A semiconductor device comprising:
a semiconductor chip having a principal surface, a rear surface on the opposite side of the principal surface, a plurality of side surfaces arranged between the principal surface and the rear surface and an electrode pad formed over the principal surface;
an adhesive patch having a first principal surface, a second principal surface on the opposite side of the first principal surface and a plurality of side surfaces betwe…

Assignees

• Renesas Electronics Corp

Inventors

• Narita Hiroaki

Classifications

• H10W72/5522

  Electricity · mapped topic

• H10W74/00

  Electricity · mapped topic

• H10W74/10

  Electricity · mapped topic

• H10W74/142

  Electricity · mapped topic

• H10W72/075

  Electricity · mapped topic