Package substrate and semiconductor package including the same
US-2024429153-A1 · Dec 26, 2024 · US
Package structure of a chip and a substrate
US8941224B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-8941224-B2 |
| Application number | US-201313853281-A |
| Country | US |
| Kind code | B2 |
| Filing date | Mar 29, 2013 |
| Priority date | Mar 29, 2013 |
| Publication date | Jan 27, 2015 |
| Grant date | Jan 27, 2015 |
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Abstract
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A package structure includes a thin chip substrate, a stabilizing material layer, a chip and a filling material. A first circuit metal layer of the substrate is inlaid into a dielectric layer and a co-plane is defined by the first circuit metal layer and the dielectric layer and is exposed from the dielectric layer. The bonding pads of the substrate are on the co-plane, have a height higher than the co-plane and connected to the first circuit metal layer. The stabilizing material layer is provided on two sides of the co-plane to define a receiving space for accommodating the chip. The filling material is injected into the receiving space to fasten the pins of the chip securely with bonding pads. Since no plastic molding is required, a total thickness of the package structure and the cost is reduced. The stabilizing material layer prevents the substrate from warping and distortion.
First claim
Opening claim text (preview).
What is claimed is: 1. A package structure of a chip and a substrate, comprising: a thin chip substrate having a first circuit metal layer, a second circuit metal layer, bonding pads and a dielectric layer, wherein the first circuit metal layer is inlaid into the dielectric layer to cooperatively define a co-plane exposed from the dielectric layer, the dielectric layer having a plurality of holes with respect to the first circuit metal layer, the second circuit metal layer being f…
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Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
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Frequently asked questions
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- What does patent US8941224B2 cover?
- A package structure includes a thin chip substrate, a stabilizing material layer, a chip and a filling material. A first circuit metal layer of the substrate is inlaid into a dielectric layer and a co-plane is defined by the first circuit metal layer and the dielectric layer and is exposed from the dielectric layer. The bonding pads of the substrate are on the co-plane, have a height higher tha…
- Who is the assignee on this patent?
- Kinsus Interconnect Tech Corp
- What technology area does this patent fall under?
- Primary CPC classification H10W70/635. Mapped technology areas include Electricity.
- When was this patent published?
- Publication date Tue Jan 27 2015 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
- What related patents are in patentsdb?
- We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).