Semiconductor devices having a trench isolation layer and methods of fabricating the same

US8941210B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-8941210-B2
Application numberUS-201414445291-A
CountryUS
Kind codeB2
Filing dateJul 29, 2014
Priority dateJan 30, 2012
Publication dateJan 27, 2015
Grant dateJan 27, 2015

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  1. Title

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  2. Abstract

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  5. First independent claim

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Abstract

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Semiconductor devices including a trench isolation layer are provided. The semiconductor device includes a substrate having a trench therein, a liner insulation layer that covers a bottom surface and sidewalls of the trench and includes micro trenches located at bottom inner corners of the liner insulation layer, a first isolating insulation layer filling the micro trenches and a lower region of the trench that are surrounded by the liner insulation layer, and a second isolating insulation layer filling the trench on the first isolating insulation layer. The liner insulation layer on sidewalls of an upper region of the trench having a thickness that gradually increases toward a bottom surface of the trench, and the liner insulation layer on sidewalls of the lower region of the trench having a thickness that is uniform. Related methods are also provided.

First claim

Opening claim text (preview).

What is claimed is: 1. A semiconductor device including a trench isolation layer, the semiconductor device comprising: a substrate having a first trench and a second trench wider than the first trench; a liner insulation layer filling the first trench, covering a bottom surface and sidewalls of the second trench, and including micro trenches located at bottom inner sidewall corners of the liner insulation layer in the second trench, the liner insulation layer on sidewalls of an…

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What does patent US8941210B2 cover?
Semiconductor devices including a trench isolation layer are provided. The semiconductor device includes a substrate having a trench therein, a liner insulation layer that covers a bottom surface and sidewalls of the trench and includes micro trenches located at bottom inner corners of the liner insulation layer, a first isolating insulation layer filling the micro trenches and a lower region o…
Who is the assignee on this patent?
Sk Hynix Inc
What technology area does this patent fall under?
Primary CPC classification H10W10/0143. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue Jan 27 2015 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).