Esd protection circuit
US-2024312981-A1 · Sep 19, 2024 · US
Semiconductor device
US8941209B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-8941209-B2 |
| Application number | US-201313897739-A |
| Country | US |
| Kind code | B2 |
| Filing date | May 20, 2013 |
| Priority date | Jun 6, 2012 |
| Publication date | Jan 27, 2015 |
| Grant date | Jan 27, 2015 |
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Abstract
Official abstract text for this publication.
Semiconductor device comprises a memory cell region, a peripheral region, and first wiring. The memory cell region includes a first isolation region, and a first active region provided so as to be divided off by the first isolation region. The peripheral region includes a second isolation region, and a second active region divided off by the first and second isolation regions and protruding from the upper surface of an insulating film located in the first and second isolation regions. The first wiring is buried in portions of a semiconductor substrate within the memory cell region and the peripheral region, so as to extend over the first and second active regions in a first direction. The first-direction width of the second active region is constant.
First claim
Opening claim text (preview).
What is claimed is: 1. A semiconductor device comprising: a memory cell region including a first isolation region, and a first active region provided so as to be divided off by the first isolation region; a peripheral region including a second isolation region, and a second active region divided off by the first and second isolation regions, the second active region being formed as a plurality of parallelogram-shaped unit patterns arranged adjacent to each other in a first direc…
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Frequently asked questions
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- What does patent US8941209B2 cover?
- Semiconductor device comprises a memory cell region, a peripheral region, and first wiring. The memory cell region includes a first isolation region, and a first active region provided so as to be divided off by the first isolation region. The peripheral region includes a second isolation region, and a second active region divided off by the first and second isolation regions and protruding fro…
- Who is the assignee on this patent?
- Elpida Memory Inc, Ps4 Luxco Sarl
- What technology area does this patent fall under?
- Primary CPC classification H10D84/00. Mapped technology areas include Electricity.
- When was this patent published?
- Publication date Tue Jan 27 2015 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
- What related patents are in patentsdb?
- We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).