Method for forming source/drain contacts
US-2024379814-A1 · Nov 14, 2024 · US
Faceted intrinsic epitaxial buffer layer for reducing short channel effects while maximizing channel stress levels
US8940595B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-8940595-B2 |
| Application number | US-201313839741-A |
| Country | US |
| Kind code | B2 |
| Filing date | Mar 15, 2013 |
| Priority date | Mar 15, 2013 |
| Publication date | Jan 27, 2015 |
| Grant date | Jan 27, 2015 |
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Abstract
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A faceted intrinsic buffer semiconductor material is deposited on sidewalls of a source trench and a drain trench by selective epitaxy. A facet adjoins each edge at which an outer sidewall of a gate spacer adjoins a sidewall of the source trench or the drain trench. A doped semiconductor material is subsequently deposited to fill the source trench and the drain trench. The doped semiconductor material can be deposited such that the facets of the intrinsic buffer semiconductor material are extended and inner sidewalls of the deposited doped semiconductor material merges in each of the source trench and the drain trench. The doped semiconductor material can subsequently grow upward. Faceted intrinsic buffer semiconductor material portions allow greater outdiffusion of dopants near faceted corners while suppressing diffusion of dopants in regions of uniform width, thereby suppressing short channel effects.
First claim
Opening claim text (preview).
What is claimed is: 1. A method of forming a semiconductor structure comprising: forming a trench having vertical sidewalls in a semiconductor substrate, wherein said vertical sidewalls extend downward from a top surface of said semiconductor substrate; depositing a stress-generating semiconductor material on said vertical sidewalls and a bottom surface of said trench by a first selective epitaxy process to form a stress-generating semiconductor material portion, wherein each ve…
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Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
- H10D62/021Primary
Electricity · mapped topic
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- What does patent US8940595B2 cover?
- A faceted intrinsic buffer semiconductor material is deposited on sidewalls of a source trench and a drain trench by selective epitaxy. A facet adjoins each edge at which an outer sidewall of a gate spacer adjoins a sidewall of the source trench or the drain trench. A doped semiconductor material is subsequently deposited to fill the source trench and the drain trench. The doped semiconductor m…
- Who is the assignee on this patent?
- IBM
- What technology area does this patent fall under?
- Primary CPC classification H10D62/021. Mapped technology areas include Electricity.
- When was this patent published?
- Publication date Tue Jan 27 2015 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
- What related patents are in patentsdb?
- We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).