Bulk FinFET ESD devices

Patent metadata

Field	Value
Publication number	US-8940588-B2
Application number	US-201414450612-A
Country	US
Kind code	B2
Filing date	Aug 4, 2014
Priority date	Nov 30, 2012
Publication date	Jan 27, 2015
Grant date	Jan 27, 2015

Abstract

Aspects of the disclosure provide a dual electrostatic discharge (ESD) protection device in fin field effect transistor (FinFET) process technology and methods of forming the same. In one embodiment, the dual ESD protection device includes: a bulk silicon substrate; a shallow trench isolation (STI) region formed over the bulk silicon substrate; a first ESD device positioned above the STI region; and a second ESD device positioned below the STI region, wherein the first ESD device conducts current above the STI region and the second ESD device conducts current below the STI region.

First claim

What is claimed is:

1. A method of manufacturing a dual ESD protection device in fin field effect transistor (FinFET) process technology, the method comprising:
providing a bulk silicon wafer substrate;
forming a plurality of fins on a top portion of the bulk silicon wafer substrate;
forming an oxide isolation region between each of the fins, the oxide isolation region including a shallow trench isolation (STI);
performing a selective epitaxial growth process to merge a port…

Assignees

• IBM

Inventors

• Gauthier Jr Robert J
• Lee Tom C
• Li Junjun
• Mitra Souvick
• Putnam Christopher Stephen

Classifications

• H10W10/17

  Electricity · mapped topic

• H10W10/014 Primary

  Electricity · mapped topic

• H10D84/853

  Electricity · mapped topic

• H10D89/811

  Electricity · mapped topic

• H10D89/713

  Electricity · mapped topic