Packaged microelectronic devices and methods for manufacturing packaged microelectronic devices

US8940581B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-8940581-B2
Application numberUS-201113298140-A
CountryUS
Kind codeB2
Filing dateNov 16, 2011
Priority dateJun 10, 2008
Publication dateJan 27, 2015
Grant dateJan 27, 2015

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  1. Title

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  2. Abstract

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  4. Key dates

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  5. First independent claim

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  7. Citations and related patents

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Abstract

Official abstract text for this publication.

Packaged microelectronic devices and methods for manufacturing packaged microelectronic devices are disclosed herein. In one embodiment, a packaged microelectronic device can include a support member, a first die attached to the support member, and a second die attached to the first die in a stacked configuration. The device can also include an attachment feature between the first and second dies. The attachment feature can be composed of a dielectric adhesive material. The attachment feature includes (a) a single, unitary structure covering at least approximately all of the back side of the second die, and (b) a plurality of interconnect structures electrically coupled to internal active features of both the first die and the second die.

First claim

Opening claim text (preview).

We claim: 1. A method for manufacturing stacked microelectronic devices, the method comprising: placing an attachment structure on a back side of a first microelectronic die, wherein the attachment structure includes a plurality of openings at least partially aligned with back side portions of electrically conductive through-substrate interconnects in the first die, and wherein the attachment structure further includes a plurality of conductive couplers formed in at least a portio…

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What does patent US8940581B2 cover?
Packaged microelectronic devices and methods for manufacturing packaged microelectronic devices are disclosed herein. In one embodiment, a packaged microelectronic device can include a support member, a first die attached to the support member, and a second die attached to the first die in a stacked configuration. The device can also include an attachment feature between the first and second di…
Who is the assignee on this patent?
Lee Choon Kuan, Chong Chin Hui, Corisis David J, and 1 more
What technology area does this patent fall under?
Primary CPC classification H10W90/00. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue Jan 27 2015 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).